/********************************************************************
 * Copyright (C) 2013-2014 Texas Instruments Incorporated.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/
#ifndef CSLR_IODELAYCONFIG_H
#define CSLR_IODELAYCONFIG_H

#ifdef __cplusplus
extern "C"
{
#endif
#include <ti/csl/cslr.h>
#include <ti/csl/tistdtypes.h>


/**************************************************************************
* Register Overlay Structure for __ALL__
**************************************************************************/
typedef struct {
    volatile Uint32 IP_REVISION;
    volatile Uint32 IP_HWINFO;
    volatile Uint32 IP_SYSCONFIG;
    volatile Uint32 CONFIG_REG_0;
    volatile Uint32 CONFIG_REG_1;
    volatile Uint32 CONFIG_REG_2;
    volatile Uint32 CONFIG_REG_3;
    volatile Uint32 CONFIG_REG_4;
    volatile Uint32 CONFIG_REG_5;
    volatile Uint32 CONFIG_REG_6;
    volatile Uint32 CONFIG_REG_7;
    volatile Uint32 CONFIG_REG_8;
    volatile Uint32 CFG_RMII_MHZ_50_CLK_IN;
    volatile Uint32 CFG_RMII_MHZ_50_CLK_OEN;
    volatile Uint32 CFG_RMII_MHZ_50_CLK_OUT;
    volatile Uint32 CFG_WAKEUP0_IN;
    volatile Uint32 CFG_WAKEUP0_OEN;
    volatile Uint32 CFG_WAKEUP0_OUT;
    volatile Uint32 CFG_WAKEUP1_IN;
    volatile Uint32 CFG_WAKEUP1_OEN;
    volatile Uint32 CFG_WAKEUP1_OUT;
    volatile Uint32 CFG_WAKEUP2_IN;
    volatile Uint32 CFG_WAKEUP2_OEN;
    volatile Uint32 CFG_WAKEUP2_OUT;
    volatile Uint32 CFG_WAKEUP3_IN;
    volatile Uint32 CFG_WAKEUP3_OEN;
    volatile Uint32 CFG_WAKEUP3_OUT;
    volatile Uint32 CFG_DCAN1_RX_IN;
    volatile Uint32 CFG_DCAN1_RX_OEN;
    volatile Uint32 CFG_DCAN1_RX_OUT;
    volatile Uint32 CFG_DCAN1_TX_IN;
    volatile Uint32 CFG_DCAN1_TX_OEN;
    volatile Uint32 CFG_DCAN1_TX_OUT;
    volatile Uint32 CFG_DCAN2_RX_IN;
    volatile Uint32 CFG_DCAN2_RX_OEN;
    volatile Uint32 CFG_DCAN2_RX_OUT;
    volatile Uint32 CFG_DCAN2_TX_IN;
    volatile Uint32 CFG_DCAN2_TX_OEN;
    volatile Uint32 CFG_DCAN2_TX_OUT;
    volatile Uint32 CFG_EMU0_IN;
    volatile Uint32 CFG_EMU0_OEN;
    volatile Uint32 CFG_EMU0_OUT;
    volatile Uint32 CFG_EMU1_IN;
    volatile Uint32 CFG_EMU1_OEN;
    volatile Uint32 CFG_EMU1_OUT;
    volatile Uint32 CFG_EMU2_IN;
    volatile Uint32 CFG_EMU2_OEN;
    volatile Uint32 CFG_EMU2_OUT;
    volatile Uint32 CFG_EMU3_IN;
    volatile Uint32 CFG_EMU3_OEN;
    volatile Uint32 CFG_EMU3_OUT;
    volatile Uint32 CFG_EMU4_IN;
    volatile Uint32 CFG_EMU4_OEN;
    volatile Uint32 CFG_EMU4_OUT;
    volatile Uint32 CFG_GPIO6_10_IN;
    volatile Uint32 CFG_GPIO6_10_OEN;
    volatile Uint32 CFG_GPIO6_10_OUT;
    volatile Uint32 CFG_GPIO6_11_IN;
    volatile Uint32 CFG_GPIO6_11_OEN;
    volatile Uint32 CFG_GPIO6_11_OUT;
    volatile Uint32 CFG_GPIO6_14_IN;
    volatile Uint32 CFG_GPIO6_14_OEN;
    volatile Uint32 CFG_GPIO6_14_OUT;
    volatile Uint32 CFG_GPIO6_15_IN;
    volatile Uint32 CFG_GPIO6_15_OEN;
    volatile Uint32 CFG_GPIO6_15_OUT;
    volatile Uint32 CFG_GPIO6_16_IN;
    volatile Uint32 CFG_GPIO6_16_OEN;
    volatile Uint32 CFG_GPIO6_16_OUT;
    volatile Uint32 CFG_GPMC_A0_IN;
    volatile Uint32 CFG_GPMC_A0_OEN;
    volatile Uint32 CFG_GPMC_A0_OUT;
    volatile Uint32 CFG_GPMC_A10_IN;
    volatile Uint32 CFG_GPMC_A10_OEN;
    volatile Uint32 CFG_GPMC_A10_OUT;
    volatile Uint32 CFG_GPMC_A11_IN;
    volatile Uint32 CFG_GPMC_A11_OEN;
    volatile Uint32 CFG_GPMC_A11_OUT;
    volatile Uint32 CFG_GPMC_A12_IN;
    volatile Uint32 CFG_GPMC_A12_OEN;
    volatile Uint32 CFG_GPMC_A12_OUT;
    volatile Uint32 CFG_GPMC_A13_IN;
    volatile Uint32 CFG_GPMC_A13_OEN;
    volatile Uint32 CFG_GPMC_A13_OUT;
    volatile Uint32 CFG_GPMC_A14_IN;
    volatile Uint32 CFG_GPMC_A14_OEN;
    volatile Uint32 CFG_GPMC_A14_OUT;
    volatile Uint32 CFG_GPMC_A15_IN;
    volatile Uint32 CFG_GPMC_A15_OEN;
    volatile Uint32 CFG_GPMC_A15_OUT;
    volatile Uint32 CFG_GPMC_A16_IN;
    volatile Uint32 CFG_GPMC_A16_OEN;
    volatile Uint32 CFG_GPMC_A16_OUT;
    volatile Uint32 CFG_GPMC_A17_IN;
    volatile Uint32 CFG_GPMC_A17_OEN;
    volatile Uint32 CFG_GPMC_A17_OUT;
    volatile Uint32 CFG_GPMC_A18_IN;
    volatile Uint32 CFG_GPMC_A18_OEN;
    volatile Uint32 CFG_GPMC_A18_OUT;
    volatile Uint32 CFG_GPMC_A19_IN;
    volatile Uint32 CFG_GPMC_A19_OEN;
    volatile Uint32 CFG_GPMC_A19_OUT;
    volatile Uint32 CFG_GPMC_A1_IN;
    volatile Uint32 CFG_GPMC_A1_OEN;
    volatile Uint32 CFG_GPMC_A1_OUT;
    volatile Uint32 CFG_GPMC_A20_IN;
    volatile Uint32 CFG_GPMC_A20_OEN;
    volatile Uint32 CFG_GPMC_A20_OUT;
    volatile Uint32 CFG_GPMC_A21_IN;
    volatile Uint32 CFG_GPMC_A21_OEN;
    volatile Uint32 CFG_GPMC_A21_OUT;
    volatile Uint32 CFG_GPMC_A22_IN;
    volatile Uint32 CFG_GPMC_A22_OEN;
    volatile Uint32 CFG_GPMC_A22_OUT;
    volatile Uint32 CFG_GPMC_A23_IN;
    volatile Uint32 CFG_GPMC_A23_OEN;
    volatile Uint32 CFG_GPMC_A23_OUT;
    volatile Uint32 CFG_GPMC_A24_IN;
    volatile Uint32 CFG_GPMC_A24_OEN;
    volatile Uint32 CFG_GPMC_A24_OUT;
    volatile Uint32 CFG_GPMC_A25_IN;
    volatile Uint32 CFG_GPMC_A25_OEN;
    volatile Uint32 CFG_GPMC_A25_OUT;
    volatile Uint32 CFG_GPMC_A26_IN;
    volatile Uint32 CFG_GPMC_A26_OEN;
    volatile Uint32 CFG_GPMC_A26_OUT;
    volatile Uint32 CFG_GPMC_A27_IN;
    volatile Uint32 CFG_GPMC_A27_OEN;
    volatile Uint32 CFG_GPMC_A27_OUT;
    volatile Uint32 CFG_GPMC_A2_IN;
    volatile Uint32 CFG_GPMC_A2_OEN;
    volatile Uint32 CFG_GPMC_A2_OUT;
    volatile Uint32 CFG_GPMC_A3_IN;
    volatile Uint32 CFG_GPMC_A3_OEN;
    volatile Uint32 CFG_GPMC_A3_OUT;
    volatile Uint32 CFG_GPMC_A4_IN;
    volatile Uint32 CFG_GPMC_A4_OEN;
    volatile Uint32 CFG_GPMC_A4_OUT;
    volatile Uint32 CFG_GPMC_A5_IN;
    volatile Uint32 CFG_GPMC_A5_OEN;
    volatile Uint32 CFG_GPMC_A5_OUT;
    volatile Uint32 CFG_GPMC_A6_IN;
    volatile Uint32 CFG_GPMC_A6_OEN;
    volatile Uint32 CFG_GPMC_A6_OUT;
    volatile Uint32 CFG_GPMC_A7_IN;
    volatile Uint32 CFG_GPMC_A7_OEN;
    volatile Uint32 CFG_GPMC_A7_OUT;
    volatile Uint32 CFG_GPMC_A8_IN;
    volatile Uint32 CFG_GPMC_A8_OEN;
    volatile Uint32 CFG_GPMC_A8_OUT;
    volatile Uint32 CFG_GPMC_A9_IN;
    volatile Uint32 CFG_GPMC_A9_OEN;
    volatile Uint32 CFG_GPMC_A9_OUT;
    volatile Uint32 CFG_GPMC_AD0_IN;
    volatile Uint32 CFG_GPMC_AD0_OEN;
    volatile Uint32 CFG_GPMC_AD0_OUT;
    volatile Uint32 CFG_GPMC_AD10_IN;
    volatile Uint32 CFG_GPMC_AD10_OEN;
    volatile Uint32 CFG_GPMC_AD10_OUT;
    volatile Uint32 CFG_GPMC_AD11_IN;
    volatile Uint32 CFG_GPMC_AD11_OEN;
    volatile Uint32 CFG_GPMC_AD11_OUT;
    volatile Uint32 CFG_GPMC_AD12_IN;
    volatile Uint32 CFG_GPMC_AD12_OEN;
    volatile Uint32 CFG_GPMC_AD12_OUT;
    volatile Uint32 CFG_GPMC_AD13_IN;
    volatile Uint32 CFG_GPMC_AD13_OEN;
    volatile Uint32 CFG_GPMC_AD13_OUT;
    volatile Uint32 CFG_GPMC_AD14_IN;
    volatile Uint32 CFG_GPMC_AD14_OEN;
    volatile Uint32 CFG_GPMC_AD14_OUT;
    volatile Uint32 CFG_GPMC_AD15_IN;
    volatile Uint32 CFG_GPMC_AD15_OEN;
    volatile Uint32 CFG_GPMC_AD15_OUT;
    volatile Uint32 CFG_GPMC_AD1_IN;
    volatile Uint32 CFG_GPMC_AD1_OEN;
    volatile Uint32 CFG_GPMC_AD1_OUT;
    volatile Uint32 CFG_GPMC_AD2_IN;
    volatile Uint32 CFG_GPMC_AD2_OEN;
    volatile Uint32 CFG_GPMC_AD2_OUT;
    volatile Uint32 CFG_GPMC_AD3_IN;
    volatile Uint32 CFG_GPMC_AD3_OEN;
    volatile Uint32 CFG_GPMC_AD3_OUT;
    volatile Uint32 CFG_GPMC_AD4_IN;
    volatile Uint32 CFG_GPMC_AD4_OEN;
    volatile Uint32 CFG_GPMC_AD4_OUT;
    volatile Uint32 CFG_GPMC_AD5_IN;
    volatile Uint32 CFG_GPMC_AD5_OEN;
    volatile Uint32 CFG_GPMC_AD5_OUT;
    volatile Uint32 CFG_GPMC_AD6_IN;
    volatile Uint32 CFG_GPMC_AD6_OEN;
    volatile Uint32 CFG_GPMC_AD6_OUT;
    volatile Uint32 CFG_GPMC_AD7_IN;
    volatile Uint32 CFG_GPMC_AD7_OEN;
    volatile Uint32 CFG_GPMC_AD7_OUT;
    volatile Uint32 CFG_GPMC_AD8_IN;
    volatile Uint32 CFG_GPMC_AD8_OEN;
    volatile Uint32 CFG_GPMC_AD8_OUT;
    volatile Uint32 CFG_GPMC_AD9_IN;
    volatile Uint32 CFG_GPMC_AD9_OEN;
    volatile Uint32 CFG_GPMC_AD9_OUT;
    volatile Uint32 CFG_GPMC_ADVN_ALE_IN;
    volatile Uint32 CFG_GPMC_ADVN_ALE_OEN;
    volatile Uint32 CFG_GPMC_ADVN_ALE_OUT;
    volatile Uint32 CFG_GPMC_BEN0_IN;
    volatile Uint32 CFG_GPMC_BEN0_OEN;
    volatile Uint32 CFG_GPMC_BEN0_OUT;
    volatile Uint32 CFG_GPMC_BEN1_IN;
    volatile Uint32 CFG_GPMC_BEN1_OEN;
    volatile Uint32 CFG_GPMC_BEN1_OUT;
    volatile Uint32 CFG_GPMC_CLK_IN;
    volatile Uint32 CFG_GPMC_CLK_OEN;
    volatile Uint32 CFG_GPMC_CLK_OUT;
    volatile Uint32 CFG_GPMC_CS0_IN;
    volatile Uint32 CFG_GPMC_CS0_OEN;
    volatile Uint32 CFG_GPMC_CS0_OUT;
    volatile Uint32 CFG_GPMC_CS1_IN;
    volatile Uint32 CFG_GPMC_CS1_OEN;
    volatile Uint32 CFG_GPMC_CS1_OUT;
    volatile Uint32 CFG_GPMC_CS2_IN;
    volatile Uint32 CFG_GPMC_CS2_OEN;
    volatile Uint32 CFG_GPMC_CS2_OUT;
    volatile Uint32 CFG_GPMC_CS3_IN;
    volatile Uint32 CFG_GPMC_CS3_OEN;
    volatile Uint32 CFG_GPMC_CS3_OUT;
    volatile Uint32 CFG_GPMC_OEN_REN_IN;
    volatile Uint32 CFG_GPMC_OEN_REN_OEN;
    volatile Uint32 CFG_GPMC_OEN_REN_OUT;
    volatile Uint32 CFG_GPMC_WAIT0_IN;
    volatile Uint32 CFG_GPMC_WAIT0_OEN;
    volatile Uint32 CFG_GPMC_WAIT0_OUT;
    volatile Uint32 CFG_GPMC_WEN_IN;
    volatile Uint32 CFG_GPMC_WEN_OEN;
    volatile Uint32 CFG_GPMC_WEN_OUT;
    volatile Uint32 CFG_MCASP1_ACLKR_IN;
    volatile Uint32 CFG_MCASP1_ACLKR_OEN;
    volatile Uint32 CFG_MCASP1_ACLKR_OUT;
    volatile Uint32 CFG_MCASP1_ACLKX_IN;
    volatile Uint32 CFG_MCASP1_ACLKX_OEN;
    volatile Uint32 CFG_MCASP1_ACLKX_OUT;
    volatile Uint32 CFG_MCASP1_AXR0_IN;
    volatile Uint32 CFG_MCASP1_AXR0_OEN;
    volatile Uint32 CFG_MCASP1_AXR0_OUT;
    volatile Uint32 CFG_MCASP1_AXR10_IN;
    volatile Uint32 CFG_MCASP1_AXR10_OEN;
    volatile Uint32 CFG_MCASP1_AXR10_OUT;
    volatile Uint32 CFG_MCASP1_AXR11_IN;
    volatile Uint32 CFG_MCASP1_AXR11_OEN;
    volatile Uint32 CFG_MCASP1_AXR11_OUT;
    volatile Uint32 CFG_MCASP1_AXR12_IN;
    volatile Uint32 CFG_MCASP1_AXR12_OEN;
    volatile Uint32 CFG_MCASP1_AXR12_OUT;
    volatile Uint32 CFG_MCASP1_AXR13_IN;
    volatile Uint32 CFG_MCASP1_AXR13_OEN;
    volatile Uint32 CFG_MCASP1_AXR13_OUT;
    volatile Uint32 CFG_MCASP1_AXR14_IN;
    volatile Uint32 CFG_MCASP1_AXR14_OEN;
    volatile Uint32 CFG_MCASP1_AXR14_OUT;
    volatile Uint32 CFG_MCASP1_AXR15_IN;
    volatile Uint32 CFG_MCASP1_AXR15_OEN;
    volatile Uint32 CFG_MCASP1_AXR15_OUT;
    volatile Uint32 CFG_MCASP1_AXR1_IN;
    volatile Uint32 CFG_MCASP1_AXR1_OEN;
    volatile Uint32 CFG_MCASP1_AXR1_OUT;
    volatile Uint32 CFG_MCASP1_AXR2_IN;
    volatile Uint32 CFG_MCASP1_AXR2_OEN;
    volatile Uint32 CFG_MCASP1_AXR2_OUT;
    volatile Uint32 CFG_MCASP1_AXR3_IN;
    volatile Uint32 CFG_MCASP1_AXR3_OEN;
    volatile Uint32 CFG_MCASP1_AXR3_OUT;
    volatile Uint32 CFG_MCASP1_AXR4_IN;
    volatile Uint32 CFG_MCASP1_AXR4_OEN;
    volatile Uint32 CFG_MCASP1_AXR4_OUT;
    volatile Uint32 CFG_MCASP1_AXR5_IN;
    volatile Uint32 CFG_MCASP1_AXR5_OEN;
    volatile Uint32 CFG_MCASP1_AXR5_OUT;
    volatile Uint32 CFG_MCASP1_AXR6_IN;
    volatile Uint32 CFG_MCASP1_AXR6_OEN;
    volatile Uint32 CFG_MCASP1_AXR6_OUT;
    volatile Uint32 CFG_MCASP1_AXR7_IN;
    volatile Uint32 CFG_MCASP1_AXR7_OEN;
    volatile Uint32 CFG_MCASP1_AXR7_OUT;
    volatile Uint32 CFG_MCASP1_AXR8_IN;
    volatile Uint32 CFG_MCASP1_AXR8_OEN;
    volatile Uint32 CFG_MCASP1_AXR8_OUT;
    volatile Uint32 CFG_MCASP1_AXR9_IN;
    volatile Uint32 CFG_MCASP1_AXR9_OEN;
    volatile Uint32 CFG_MCASP1_AXR9_OUT;
    volatile Uint32 CFG_MCASP1_FSR_IN;
    volatile Uint32 CFG_MCASP1_FSR_OEN;
    volatile Uint32 CFG_MCASP1_FSR_OUT;
    volatile Uint32 CFG_MCASP1_FSX_IN;
    volatile Uint32 CFG_MCASP1_FSX_OEN;
    volatile Uint32 CFG_MCASP1_FSX_OUT;
    volatile Uint32 CFG_MCASP2_ACLKR_IN;
    volatile Uint32 CFG_MCASP2_ACLKR_OEN;
    volatile Uint32 CFG_MCASP2_ACLKR_OUT;
    volatile Uint32 CFG_MCASP2_ACLKX_IN;
    volatile Uint32 CFG_MCASP2_ACLKX_OEN;
    volatile Uint32 CFG_MCASP2_ACLKX_OUT;
    volatile Uint32 CFG_MCASP2_AXR0_IN;
    volatile Uint32 CFG_MCASP2_AXR0_OEN;
    volatile Uint32 CFG_MCASP2_AXR0_OUT;
    volatile Uint32 CFG_MCASP2_AXR1_IN;
    volatile Uint32 CFG_MCASP2_AXR1_OEN;
    volatile Uint32 CFG_MCASP2_AXR1_OUT;
    volatile Uint32 CFG_MCASP2_AXR2_IN;
    volatile Uint32 CFG_MCASP2_AXR2_OEN;
    volatile Uint32 CFG_MCASP2_AXR2_OUT;
    volatile Uint32 CFG_MCASP2_AXR3_IN;
    volatile Uint32 CFG_MCASP2_AXR3_OEN;
    volatile Uint32 CFG_MCASP2_AXR3_OUT;
    volatile Uint32 CFG_MCASP2_AXR4_IN;
    volatile Uint32 CFG_MCASP2_AXR4_OEN;
    volatile Uint32 CFG_MCASP2_AXR4_OUT;
    volatile Uint32 CFG_MCASP2_AXR5_IN;
    volatile Uint32 CFG_MCASP2_AXR5_OEN;
    volatile Uint32 CFG_MCASP2_AXR5_OUT;
    volatile Uint32 CFG_MCASP2_AXR6_IN;
    volatile Uint32 CFG_MCASP2_AXR6_OEN;
    volatile Uint32 CFG_MCASP2_AXR6_OUT;
    volatile Uint32 CFG_MCASP2_AXR7_IN;
    volatile Uint32 CFG_MCASP2_AXR7_OEN;
    volatile Uint32 CFG_MCASP2_AXR7_OUT;
    volatile Uint32 CFG_MCASP2_FSR_IN;
    volatile Uint32 CFG_MCASP2_FSR_OEN;
    volatile Uint32 CFG_MCASP2_FSR_OUT;
    volatile Uint32 CFG_MCASP2_FSX_IN;
    volatile Uint32 CFG_MCASP2_FSX_OEN;
    volatile Uint32 CFG_MCASP2_FSX_OUT;
    volatile Uint32 CFG_MCASP3_ACLKX_IN;
    volatile Uint32 CFG_MCASP3_ACLKX_OEN;
    volatile Uint32 CFG_MCASP3_ACLKX_OUT;
    volatile Uint32 CFG_MCASP3_AXR0_IN;
    volatile Uint32 CFG_MCASP3_AXR0_OEN;
    volatile Uint32 CFG_MCASP3_AXR0_OUT;
    volatile Uint32 CFG_MCASP3_AXR1_IN;
    volatile Uint32 CFG_MCASP3_AXR1_OEN;
    volatile Uint32 CFG_MCASP3_AXR1_OUT;
    volatile Uint32 CFG_MCASP3_FSX_IN;
    volatile Uint32 CFG_MCASP3_FSX_OEN;
    volatile Uint32 CFG_MCASP3_FSX_OUT;
    volatile Uint32 CFG_MCASP4_ACLKX_IN;
    volatile Uint32 CFG_MCASP4_ACLKX_OEN;
    volatile Uint32 CFG_MCASP4_ACLKX_OUT;
    volatile Uint32 CFG_MCASP4_AXR0_IN;
    volatile Uint32 CFG_MCASP4_AXR0_OEN;
    volatile Uint32 CFG_MCASP4_AXR0_OUT;
    volatile Uint32 CFG_MCASP4_AXR1_IN;
    volatile Uint32 CFG_MCASP4_AXR1_OEN;
    volatile Uint32 CFG_MCASP4_AXR1_OUT;
    volatile Uint32 CFG_MCASP4_FSX_IN;
    volatile Uint32 CFG_MCASP4_FSX_OEN;
    volatile Uint32 CFG_MCASP4_FSX_OUT;
    volatile Uint32 CFG_MCASP5_ACLKX_IN;
    volatile Uint32 CFG_MCASP5_ACLKX_OEN;
    volatile Uint32 CFG_MCASP5_ACLKX_OUT;
    volatile Uint32 CFG_MCASP5_AXR0_IN;
    volatile Uint32 CFG_MCASP5_AXR0_OEN;
    volatile Uint32 CFG_MCASP5_AXR0_OUT;
    volatile Uint32 CFG_MCASP5_AXR1_IN;
    volatile Uint32 CFG_MCASP5_AXR1_OEN;
    volatile Uint32 CFG_MCASP5_AXR1_OUT;
    volatile Uint32 CFG_MCASP5_FSX_IN;
    volatile Uint32 CFG_MCASP5_FSX_OEN;
    volatile Uint32 CFG_MCASP5_FSX_OUT;
    volatile Uint32 CFG_MDIO_D_IN;
    volatile Uint32 CFG_MDIO_D_OEN;
    volatile Uint32 CFG_MDIO_D_OUT;
    volatile Uint32 CFG_MDIO_MCLK_IN;
    volatile Uint32 CFG_MDIO_MCLK_OEN;
    volatile Uint32 CFG_MDIO_MCLK_OUT;
    volatile Uint32 CFG_MLBP_CLK_N_IN;
    volatile Uint32 CFG_MLBP_CLK_N_OEN;
    volatile Uint32 CFG_MLBP_CLK_N_OUT;
    volatile Uint32 CFG_MLBP_CLK_P_IN;
    volatile Uint32 CFG_MLBP_CLK_P_OEN;
    volatile Uint32 CFG_MLBP_CLK_P_OUT;
    volatile Uint32 CFG_MLBP_DAT_N_IN;
    volatile Uint32 CFG_MLBP_DAT_N_OEN;
    volatile Uint32 CFG_MLBP_DAT_N_OUT;
    volatile Uint32 CFG_MLBP_DAT_P_IN;
    volatile Uint32 CFG_MLBP_DAT_P_OEN;
    volatile Uint32 CFG_MLBP_DAT_P_OUT;
    volatile Uint32 CFG_MLBP_SIG_N_IN;
    volatile Uint32 CFG_MLBP_SIG_N_OEN;
    volatile Uint32 CFG_MLBP_SIG_N_OUT;
    volatile Uint32 CFG_MLBP_SIG_P_IN;
    volatile Uint32 CFG_MLBP_SIG_P_OEN;
    volatile Uint32 CFG_MLBP_SIG_P_OUT;
    volatile Uint32 CFG_MMC1_CLK_IN;
    volatile Uint32 CFG_MMC1_CLK_OEN;
    volatile Uint32 CFG_MMC1_CLK_OUT;
    volatile Uint32 CFG_MMC1_CMD_IN;
    volatile Uint32 CFG_MMC1_CMD_OEN;
    volatile Uint32 CFG_MMC1_CMD_OUT;
    volatile Uint32 CFG_MMC1_DAT0_IN;
    volatile Uint32 CFG_MMC1_DAT0_OEN;
    volatile Uint32 CFG_MMC1_DAT0_OUT;
    volatile Uint32 CFG_MMC1_DAT1_IN;
    volatile Uint32 CFG_MMC1_DAT1_OEN;
    volatile Uint32 CFG_MMC1_DAT1_OUT;
    volatile Uint32 CFG_MMC1_DAT2_IN;
    volatile Uint32 CFG_MMC1_DAT2_OEN;
    volatile Uint32 CFG_MMC1_DAT2_OUT;
    volatile Uint32 CFG_MMC1_DAT3_IN;
    volatile Uint32 CFG_MMC1_DAT3_OEN;
    volatile Uint32 CFG_MMC1_DAT3_OUT;
    volatile Uint32 CFG_MMC1_SDCD_IN;
    volatile Uint32 CFG_MMC1_SDCD_OEN;
    volatile Uint32 CFG_MMC1_SDCD_OUT;
    volatile Uint32 CFG_MMC1_SDWP_IN;
    volatile Uint32 CFG_MMC1_SDWP_OEN;
    volatile Uint32 CFG_MMC1_SDWP_OUT;
    volatile Uint32 CFG_MMC3_CLK_IN;
    volatile Uint32 CFG_MMC3_CLK_OEN;
    volatile Uint32 CFG_MMC3_CLK_OUT;
    volatile Uint32 CFG_MMC3_CMD_IN;
    volatile Uint32 CFG_MMC3_CMD_OEN;
    volatile Uint32 CFG_MMC3_CMD_OUT;
    volatile Uint32 CFG_MMC3_DAT0_IN;
    volatile Uint32 CFG_MMC3_DAT0_OEN;
    volatile Uint32 CFG_MMC3_DAT0_OUT;
    volatile Uint32 CFG_MMC3_DAT1_IN;
    volatile Uint32 CFG_MMC3_DAT1_OEN;
    volatile Uint32 CFG_MMC3_DAT1_OUT;
    volatile Uint32 CFG_MMC3_DAT2_IN;
    volatile Uint32 CFG_MMC3_DAT2_OEN;
    volatile Uint32 CFG_MMC3_DAT2_OUT;
    volatile Uint32 CFG_MMC3_DAT3_IN;
    volatile Uint32 CFG_MMC3_DAT3_OEN;
    volatile Uint32 CFG_MMC3_DAT3_OUT;
    volatile Uint32 CFG_MMC3_DAT4_IN;
    volatile Uint32 CFG_MMC3_DAT4_OEN;
    volatile Uint32 CFG_MMC3_DAT4_OUT;
    volatile Uint32 CFG_MMC3_DAT5_IN;
    volatile Uint32 CFG_MMC3_DAT5_OEN;
    volatile Uint32 CFG_MMC3_DAT5_OUT;
    volatile Uint32 CFG_MMC3_DAT6_IN;
    volatile Uint32 CFG_MMC3_DAT6_OEN;
    volatile Uint32 CFG_MMC3_DAT6_OUT;
    volatile Uint32 CFG_MMC3_DAT7_IN;
    volatile Uint32 CFG_MMC3_DAT7_OEN;
    volatile Uint32 CFG_MMC3_DAT7_OUT;
    volatile Uint32 CFG_RGMII0_RXC_IN;
    volatile Uint32 CFG_RGMII0_RXC_OEN;
    volatile Uint32 CFG_RGMII0_RXC_OUT;
    volatile Uint32 CFG_RGMII0_RXCTL_IN;
    volatile Uint32 CFG_RGMII0_RXCTL_OEN;
    volatile Uint32 CFG_RGMII0_RXCTL_OUT;
    volatile Uint32 CFG_RGMII0_RXD0_IN;
    volatile Uint32 CFG_RGMII0_RXD0_OEN;
    volatile Uint32 CFG_RGMII0_RXD0_OUT;
    volatile Uint32 CFG_RGMII0_RXD1_IN;
    volatile Uint32 CFG_RGMII0_RXD1_OEN;
    volatile Uint32 CFG_RGMII0_RXD1_OUT;
    volatile Uint32 CFG_RGMII0_RXD2_IN;
    volatile Uint32 CFG_RGMII0_RXD2_OEN;
    volatile Uint32 CFG_RGMII0_RXD2_OUT;
    volatile Uint32 CFG_RGMII0_RXD3_IN;
    volatile Uint32 CFG_RGMII0_RXD3_OEN;
    volatile Uint32 CFG_RGMII0_RXD3_OUT;
    volatile Uint32 CFG_RGMII0_TXC_IN;
    volatile Uint32 CFG_RGMII0_TXC_OEN;
    volatile Uint32 CFG_RGMII0_TXC_OUT;
    volatile Uint32 CFG_RGMII0_TXCTL_IN;
    volatile Uint32 CFG_RGMII0_TXCTL_OEN;
    volatile Uint32 CFG_RGMII0_TXCTL_OUT;
    volatile Uint32 CFG_RGMII0_TXD0_IN;
    volatile Uint32 CFG_RGMII0_TXD0_OEN;
    volatile Uint32 CFG_RGMII0_TXD0_OUT;
    volatile Uint32 CFG_RGMII0_TXD1_IN;
    volatile Uint32 CFG_RGMII0_TXD1_OEN;
    volatile Uint32 CFG_RGMII0_TXD1_OUT;
    volatile Uint32 CFG_RGMII0_TXD2_IN;
    volatile Uint32 CFG_RGMII0_TXD2_OEN;
    volatile Uint32 CFG_RGMII0_TXD2_OUT;
    volatile Uint32 CFG_RGMII0_TXD3_IN;
    volatile Uint32 CFG_RGMII0_TXD3_OEN;
    volatile Uint32 CFG_RGMII0_TXD3_OUT;
    volatile Uint32 CFG_RTCK_IN;
    volatile Uint32 CFG_RTCK_OEN;
    volatile Uint32 CFG_RTCK_OUT;
    volatile Uint32 CFG_SPI1_CS0_IN;
    volatile Uint32 CFG_SPI1_CS0_OEN;
    volatile Uint32 CFG_SPI1_CS0_OUT;
    volatile Uint32 CFG_SPI1_CS1_IN;
    volatile Uint32 CFG_SPI1_CS1_OEN;
    volatile Uint32 CFG_SPI1_CS1_OUT;
    volatile Uint32 CFG_SPI1_CS2_IN;
    volatile Uint32 CFG_SPI1_CS2_OEN;
    volatile Uint32 CFG_SPI1_CS2_OUT;
    volatile Uint32 CFG_SPI1_CS3_IN;
    volatile Uint32 CFG_SPI1_CS3_OEN;
    volatile Uint32 CFG_SPI1_CS3_OUT;
    volatile Uint32 CFG_SPI1_D0_IN;
    volatile Uint32 CFG_SPI1_D0_OEN;
    volatile Uint32 CFG_SPI1_D0_OUT;
    volatile Uint32 CFG_SPI1_D1_IN;
    volatile Uint32 CFG_SPI1_D1_OEN;
    volatile Uint32 CFG_SPI1_D1_OUT;
    volatile Uint32 CFG_SPI1_SCLK_IN;
    volatile Uint32 CFG_SPI1_SCLK_OEN;
    volatile Uint32 CFG_SPI1_SCLK_OUT;
    volatile Uint32 CFG_SPI2_CS0_IN;
    volatile Uint32 CFG_SPI2_CS0_OEN;
    volatile Uint32 CFG_SPI2_CS0_OUT;
    volatile Uint32 CFG_SPI2_D0_IN;
    volatile Uint32 CFG_SPI2_D0_OEN;
    volatile Uint32 CFG_SPI2_D0_OUT;
    volatile Uint32 CFG_SPI2_D1_IN;
    volatile Uint32 CFG_SPI2_D1_OEN;
    volatile Uint32 CFG_SPI2_D1_OUT;
    volatile Uint32 CFG_SPI2_SCLK_IN;
    volatile Uint32 CFG_SPI2_SCLK_OEN;
    volatile Uint32 CFG_SPI2_SCLK_OUT;
    volatile Uint32 CFG_TDI_IN;
    volatile Uint32 CFG_TDI_OEN;
    volatile Uint32 CFG_TDI_OUT;
    volatile Uint32 CFG_TDO_IN;
    volatile Uint32 CFG_TDO_OEN;
    volatile Uint32 CFG_TDO_OUT;
    volatile Uint32 CFG_TMS_IN;
    volatile Uint32 CFG_TMS_OEN;
    volatile Uint32 CFG_TMS_OUT;
    volatile Uint32 CFG_TRSTN_IN;
    volatile Uint32 CFG_TRSTN_OEN;
    volatile Uint32 CFG_TRSTN_OUT;
    volatile Uint32 CFG_UART1_CTSN_IN;
    volatile Uint32 CFG_UART1_CTSN_OEN;
    volatile Uint32 CFG_UART1_CTSN_OUT;
    volatile Uint32 CFG_UART1_RTSN_IN;
    volatile Uint32 CFG_UART1_RTSN_OEN;
    volatile Uint32 CFG_UART1_RTSN_OUT;
    volatile Uint32 CFG_UART1_RXD_IN;
    volatile Uint32 CFG_UART1_RXD_OEN;
    volatile Uint32 CFG_UART1_RXD_OUT;
    volatile Uint32 CFG_UART1_TXD_IN;
    volatile Uint32 CFG_UART1_TXD_OEN;
    volatile Uint32 CFG_UART1_TXD_OUT;
    volatile Uint32 CFG_UART2_CTSN_IN;
    volatile Uint32 CFG_UART2_CTSN_OEN;
    volatile Uint32 CFG_UART2_CTSN_OUT;
    volatile Uint32 CFG_UART2_RTSN_IN;
    volatile Uint32 CFG_UART2_RTSN_OEN;
    volatile Uint32 CFG_UART2_RTSN_OUT;
    volatile Uint32 CFG_UART2_RXD_IN;
    volatile Uint32 CFG_UART2_RXD_OEN;
    volatile Uint32 CFG_UART2_RXD_OUT;
    volatile Uint32 CFG_UART2_TXD_IN;
    volatile Uint32 CFG_UART2_TXD_OEN;
    volatile Uint32 CFG_UART2_TXD_OUT;
    volatile Uint32 CFG_UART3_RXD_IN;
    volatile Uint32 CFG_UART3_RXD_OEN;
    volatile Uint32 CFG_UART3_RXD_OUT;
    volatile Uint32 CFG_UART3_TXD_IN;
    volatile Uint32 CFG_UART3_TXD_OEN;
    volatile Uint32 CFG_UART3_TXD_OUT;
    volatile Uint32 CFG_USB1_DRVVBUS_IN;
    volatile Uint32 CFG_USB1_DRVVBUS_OEN;
    volatile Uint32 CFG_USB1_DRVVBUS_OUT;
    volatile Uint32 CFG_USB2_DRVVBUS_IN;
    volatile Uint32 CFG_USB2_DRVVBUS_OEN;
    volatile Uint32 CFG_USB2_DRVVBUS_OUT;
    volatile Uint32 CFG_VIN1A_CLK0_IN;
    volatile Uint32 CFG_VIN1A_CLK0_OEN;
    volatile Uint32 CFG_VIN1A_CLK0_OUT;
    volatile Uint32 CFG_VIN1A_D0_IN;
    volatile Uint32 CFG_VIN1A_D0_OEN;
    volatile Uint32 CFG_VIN1A_D0_OUT;
    volatile Uint32 CFG_VIN1A_D10_IN;
    volatile Uint32 CFG_VIN1A_D10_OEN;
    volatile Uint32 CFG_VIN1A_D10_OUT;
    volatile Uint32 CFG_VIN1A_D11_IN;
    volatile Uint32 CFG_VIN1A_D11_OEN;
    volatile Uint32 CFG_VIN1A_D11_OUT;
    volatile Uint32 CFG_VIN1A_D12_IN;
    volatile Uint32 CFG_VIN1A_D12_OEN;
    volatile Uint32 CFG_VIN1A_D12_OUT;
    volatile Uint32 CFG_VIN1A_D13_IN;
    volatile Uint32 CFG_VIN1A_D13_OEN;
    volatile Uint32 CFG_VIN1A_D13_OUT;
    volatile Uint32 CFG_VIN1A_D14_IN;
    volatile Uint32 CFG_VIN1A_D14_OEN;
    volatile Uint32 CFG_VIN1A_D14_OUT;
    volatile Uint32 CFG_VIN1A_D15_IN;
    volatile Uint32 CFG_VIN1A_D15_OEN;
    volatile Uint32 CFG_VIN1A_D15_OUT;
    volatile Uint32 CFG_VIN1A_D16_IN;
    volatile Uint32 CFG_VIN1A_D16_OEN;
    volatile Uint32 CFG_VIN1A_D16_OUT;
    volatile Uint32 CFG_VIN1A_D17_IN;
    volatile Uint32 CFG_VIN1A_D17_OEN;
    volatile Uint32 CFG_VIN1A_D17_OUT;
    volatile Uint32 CFG_VIN1A_D18_IN;
    volatile Uint32 CFG_VIN1A_D18_OEN;
    volatile Uint32 CFG_VIN1A_D18_OUT;
    volatile Uint32 CFG_VIN1A_D19_IN;
    volatile Uint32 CFG_VIN1A_D19_OEN;
    volatile Uint32 CFG_VIN1A_D19_OUT;
    volatile Uint32 CFG_VIN1A_D1_IN;
    volatile Uint32 CFG_VIN1A_D1_OEN;
    volatile Uint32 CFG_VIN1A_D1_OUT;
    volatile Uint32 CFG_VIN1A_D20_IN;
    volatile Uint32 CFG_VIN1A_D20_OEN;
    volatile Uint32 CFG_VIN1A_D20_OUT;
    volatile Uint32 CFG_VIN1A_D21_IN;
    volatile Uint32 CFG_VIN1A_D21_OEN;
    volatile Uint32 CFG_VIN1A_D21_OUT;
    volatile Uint32 CFG_VIN1A_D22_IN;
    volatile Uint32 CFG_VIN1A_D22_OEN;
    volatile Uint32 CFG_VIN1A_D22_OUT;
    volatile Uint32 CFG_VIN1A_D23_IN;
    volatile Uint32 CFG_VIN1A_D23_OEN;
    volatile Uint32 CFG_VIN1A_D23_OUT;
    volatile Uint32 CFG_VIN1A_D2_IN;
    volatile Uint32 CFG_VIN1A_D2_OEN;
    volatile Uint32 CFG_VIN1A_D2_OUT;
    volatile Uint32 CFG_VIN1A_D3_IN;
    volatile Uint32 CFG_VIN1A_D3_OEN;
    volatile Uint32 CFG_VIN1A_D3_OUT;
    volatile Uint32 CFG_VIN1A_D4_IN;
    volatile Uint32 CFG_VIN1A_D4_OEN;
    volatile Uint32 CFG_VIN1A_D4_OUT;
    volatile Uint32 CFG_VIN1A_D5_IN;
    volatile Uint32 CFG_VIN1A_D5_OEN;
    volatile Uint32 CFG_VIN1A_D5_OUT;
    volatile Uint32 CFG_VIN1A_D6_IN;
    volatile Uint32 CFG_VIN1A_D6_OEN;
    volatile Uint32 CFG_VIN1A_D6_OUT;
    volatile Uint32 CFG_VIN1A_D7_IN;
    volatile Uint32 CFG_VIN1A_D7_OEN;
    volatile Uint32 CFG_VIN1A_D7_OUT;
    volatile Uint32 CFG_VIN1A_D8_IN;
    volatile Uint32 CFG_VIN1A_D8_OEN;
    volatile Uint32 CFG_VIN1A_D8_OUT;
    volatile Uint32 CFG_VIN1A_D9_IN;
    volatile Uint32 CFG_VIN1A_D9_OEN;
    volatile Uint32 CFG_VIN1A_D9_OUT;
    volatile Uint32 CFG_VIN1A_DE0_IN;
    volatile Uint32 CFG_VIN1A_DE0_OEN;
    volatile Uint32 CFG_VIN1A_DE0_OUT;
    volatile Uint32 CFG_VIN1A_FLD0_IN;
    volatile Uint32 CFG_VIN1A_FLD0_OEN;
    volatile Uint32 CFG_VIN1A_FLD0_OUT;
    volatile Uint32 CFG_VIN1A_HSYNC0_IN;
    volatile Uint32 CFG_VIN1A_HSYNC0_OEN;
    volatile Uint32 CFG_VIN1A_HSYNC0_OUT;
    volatile Uint32 CFG_VIN1A_VSYNC0_IN;
    volatile Uint32 CFG_VIN1A_VSYNC0_OEN;
    volatile Uint32 CFG_VIN1A_VSYNC0_OUT;
    volatile Uint32 CFG_VIN1B_CLK1_IN;
    volatile Uint32 CFG_VIN1B_CLK1_OEN;
    volatile Uint32 CFG_VIN1B_CLK1_OUT;
    volatile Uint32 CFG_VIN2A_CLK0_IN;
    volatile Uint32 CFG_VIN2A_CLK0_OEN;
    volatile Uint32 CFG_VIN2A_CLK0_OUT;
    volatile Uint32 CFG_VIN2A_D0_IN;
    volatile Uint32 CFG_VIN2A_D0_OEN;
    volatile Uint32 CFG_VIN2A_D0_OUT;
    volatile Uint32 CFG_VIN2A_D10_IN;
    volatile Uint32 CFG_VIN2A_D10_OEN;
    volatile Uint32 CFG_VIN2A_D10_OUT;
    volatile Uint32 CFG_VIN2A_D11_IN;
    volatile Uint32 CFG_VIN2A_D11_OEN;
    volatile Uint32 CFG_VIN2A_D11_OUT;
    volatile Uint32 CFG_VIN2A_D12_IN;
    volatile Uint32 CFG_VIN2A_D12_OEN;
    volatile Uint32 CFG_VIN2A_D12_OUT;
    volatile Uint32 CFG_VIN2A_D13_IN;
    volatile Uint32 CFG_VIN2A_D13_OEN;
    volatile Uint32 CFG_VIN2A_D13_OUT;
    volatile Uint32 CFG_VIN2A_D14_IN;
    volatile Uint32 CFG_VIN2A_D14_OEN;
    volatile Uint32 CFG_VIN2A_D14_OUT;
    volatile Uint32 CFG_VIN2A_D15_IN;
    volatile Uint32 CFG_VIN2A_D15_OEN;
    volatile Uint32 CFG_VIN2A_D15_OUT;
    volatile Uint32 CFG_VIN2A_D16_IN;
    volatile Uint32 CFG_VIN2A_D16_OEN;
    volatile Uint32 CFG_VIN2A_D16_OUT;
    volatile Uint32 CFG_VIN2A_D17_IN;
    volatile Uint32 CFG_VIN2A_D17_OEN;
    volatile Uint32 CFG_VIN2A_D17_OUT;
    volatile Uint32 CFG_VIN2A_D18_IN;
    volatile Uint32 CFG_VIN2A_D18_OEN;
    volatile Uint32 CFG_VIN2A_D18_OUT;
    volatile Uint32 CFG_VIN2A_D19_IN;
    volatile Uint32 CFG_VIN2A_D19_OEN;
    volatile Uint32 CFG_VIN2A_D19_OUT;
    volatile Uint32 CFG_VIN2A_D1_IN;
    volatile Uint32 CFG_VIN2A_D1_OEN;
    volatile Uint32 CFG_VIN2A_D1_OUT;
    volatile Uint32 CFG_VIN2A_D20_IN;
    volatile Uint32 CFG_VIN2A_D20_OEN;
    volatile Uint32 CFG_VIN2A_D20_OUT;
    volatile Uint32 CFG_VIN2A_D21_IN;
    volatile Uint32 CFG_VIN2A_D21_OEN;
    volatile Uint32 CFG_VIN2A_D21_OUT;
    volatile Uint32 CFG_VIN2A_D22_IN;
    volatile Uint32 CFG_VIN2A_D22_OEN;
    volatile Uint32 CFG_VIN2A_D22_OUT;
    volatile Uint32 CFG_VIN2A_D23_IN;
    volatile Uint32 CFG_VIN2A_D23_OEN;
    volatile Uint32 CFG_VIN2A_D23_OUT;
    volatile Uint32 CFG_VIN2A_D2_IN;
    volatile Uint32 CFG_VIN2A_D2_OEN;
    volatile Uint32 CFG_VIN2A_D2_OUT;
    volatile Uint32 CFG_VIN2A_D3_IN;
    volatile Uint32 CFG_VIN2A_D3_OEN;
    volatile Uint32 CFG_VIN2A_D3_OUT;
    volatile Uint32 CFG_VIN2A_D4_IN;
    volatile Uint32 CFG_VIN2A_D4_OEN;
    volatile Uint32 CFG_VIN2A_D4_OUT;
    volatile Uint32 CFG_VIN2A_D5_IN;
    volatile Uint32 CFG_VIN2A_D5_OEN;
    volatile Uint32 CFG_VIN2A_D5_OUT;
    volatile Uint32 CFG_VIN2A_D6_IN;
    volatile Uint32 CFG_VIN2A_D6_OEN;
    volatile Uint32 CFG_VIN2A_D6_OUT;
    volatile Uint32 CFG_VIN2A_D7_IN;
    volatile Uint32 CFG_VIN2A_D7_OEN;
    volatile Uint32 CFG_VIN2A_D7_OUT;
    volatile Uint32 CFG_VIN2A_D8_IN;
    volatile Uint32 CFG_VIN2A_D8_OEN;
    volatile Uint32 CFG_VIN2A_D8_OUT;
    volatile Uint32 CFG_VIN2A_D9_IN;
    volatile Uint32 CFG_VIN2A_D9_OEN;
    volatile Uint32 CFG_VIN2A_D9_OUT;
    volatile Uint32 CFG_VIN2A_DE0_IN;
    volatile Uint32 CFG_VIN2A_DE0_OEN;
    volatile Uint32 CFG_VIN2A_DE0_OUT;
    volatile Uint32 CFG_VIN2A_FLD0_IN;
    volatile Uint32 CFG_VIN2A_FLD0_OEN;
    volatile Uint32 CFG_VIN2A_FLD0_OUT;
    volatile Uint32 CFG_VIN2A_HSYNC0_IN;
    volatile Uint32 CFG_VIN2A_HSYNC0_OEN;
    volatile Uint32 CFG_VIN2A_HSYNC0_OUT;
    volatile Uint32 CFG_VIN2A_VSYNC0_IN;
    volatile Uint32 CFG_VIN2A_VSYNC0_OEN;
    volatile Uint32 CFG_VIN2A_VSYNC0_OUT;
    volatile Uint32 CFG_VOUT1_CLK_IN;
    volatile Uint32 CFG_VOUT1_CLK_OEN;
    volatile Uint32 CFG_VOUT1_CLK_OUT;
    volatile Uint32 CFG_VOUT1_D0_IN;
    volatile Uint32 CFG_VOUT1_D0_OEN;
    volatile Uint32 CFG_VOUT1_D0_OUT;
    volatile Uint32 CFG_VOUT1_D10_IN;
    volatile Uint32 CFG_VOUT1_D10_OEN;
    volatile Uint32 CFG_VOUT1_D10_OUT;
    volatile Uint32 CFG_VOUT1_D11_IN;
    volatile Uint32 CFG_VOUT1_D11_OEN;
    volatile Uint32 CFG_VOUT1_D11_OUT;
    volatile Uint32 CFG_VOUT1_D12_IN;
    volatile Uint32 CFG_VOUT1_D12_OEN;
    volatile Uint32 CFG_VOUT1_D12_OUT;
    volatile Uint32 CFG_VOUT1_D13_IN;
    volatile Uint32 CFG_VOUT1_D13_OEN;
    volatile Uint32 CFG_VOUT1_D13_OUT;
    volatile Uint32 CFG_VOUT1_D14_IN;
    volatile Uint32 CFG_VOUT1_D14_OEN;
    volatile Uint32 CFG_VOUT1_D14_OUT;
    volatile Uint32 CFG_VOUT1_D15_IN;
    volatile Uint32 CFG_VOUT1_D15_OEN;
    volatile Uint32 CFG_VOUT1_D15_OUT;
    volatile Uint32 CFG_VOUT1_D16_IN;
    volatile Uint32 CFG_VOUT1_D16_OEN;
    volatile Uint32 CFG_VOUT1_D16_OUT;
    volatile Uint32 CFG_VOUT1_D17_IN;
    volatile Uint32 CFG_VOUT1_D17_OEN;
    volatile Uint32 CFG_VOUT1_D17_OUT;
    volatile Uint32 CFG_VOUT1_D18_IN;
    volatile Uint32 CFG_VOUT1_D18_OEN;
    volatile Uint32 CFG_VOUT1_D18_OUT;
    volatile Uint32 CFG_VOUT1_D19_IN;
    volatile Uint32 CFG_VOUT1_D19_OEN;
    volatile Uint32 CFG_VOUT1_D19_OUT;
    volatile Uint32 CFG_VOUT1_D1_IN;
    volatile Uint32 CFG_VOUT1_D1_OEN;
    volatile Uint32 CFG_VOUT1_D1_OUT;
    volatile Uint32 CFG_VOUT1_D20_IN;
    volatile Uint32 CFG_VOUT1_D20_OEN;
    volatile Uint32 CFG_VOUT1_D20_OUT;
    volatile Uint32 CFG_VOUT1_D21_IN;
    volatile Uint32 CFG_VOUT1_D21_OEN;
    volatile Uint32 CFG_VOUT1_D21_OUT;
    volatile Uint32 CFG_VOUT1_D22_IN;
    volatile Uint32 CFG_VOUT1_D22_OEN;
    volatile Uint32 CFG_VOUT1_D22_OUT;
    volatile Uint32 CFG_VOUT1_D23_IN;
    volatile Uint32 CFG_VOUT1_D23_OEN;
    volatile Uint32 CFG_VOUT1_D23_OUT;
    volatile Uint32 CFG_VOUT1_D2_IN;
    volatile Uint32 CFG_VOUT1_D2_OEN;
    volatile Uint32 CFG_VOUT1_D2_OUT;
    volatile Uint32 CFG_VOUT1_D3_IN;
    volatile Uint32 CFG_VOUT1_D3_OEN;
    volatile Uint32 CFG_VOUT1_D3_OUT;
    volatile Uint32 CFG_VOUT1_D4_IN;
    volatile Uint32 CFG_VOUT1_D4_OEN;
    volatile Uint32 CFG_VOUT1_D4_OUT;
    volatile Uint32 CFG_VOUT1_D5_IN;
    volatile Uint32 CFG_VOUT1_D5_OEN;
    volatile Uint32 CFG_VOUT1_D5_OUT;
    volatile Uint32 CFG_VOUT1_D6_IN;
    volatile Uint32 CFG_VOUT1_D6_OEN;
    volatile Uint32 CFG_VOUT1_D6_OUT;
    volatile Uint32 CFG_VOUT1_D7_IN;
    volatile Uint32 CFG_VOUT1_D7_OEN;
    volatile Uint32 CFG_VOUT1_D7_OUT;
    volatile Uint32 CFG_VOUT1_D8_IN;
    volatile Uint32 CFG_VOUT1_D8_OEN;
    volatile Uint32 CFG_VOUT1_D8_OUT;
    volatile Uint32 CFG_VOUT1_D9_IN;
    volatile Uint32 CFG_VOUT1_D9_OEN;
    volatile Uint32 CFG_VOUT1_D9_OUT;
    volatile Uint32 CFG_VOUT1_DE_IN;
    volatile Uint32 CFG_VOUT1_DE_OEN;
    volatile Uint32 CFG_VOUT1_DE_OUT;
    volatile Uint32 CFG_VOUT1_FLD_IN;
    volatile Uint32 CFG_VOUT1_FLD_OEN;
    volatile Uint32 CFG_VOUT1_FLD_OUT;
    volatile Uint32 CFG_VOUT1_HSYNC_IN;
    volatile Uint32 CFG_VOUT1_HSYNC_OEN;
    volatile Uint32 CFG_VOUT1_HSYNC_OUT;
    volatile Uint32 CFG_VOUT1_VSYNC_IN;
    volatile Uint32 CFG_VOUT1_VSYNC_OEN;
    volatile Uint32 CFG_VOUT1_VSYNC_OUT;
    volatile Uint32 CFG_XREF_CLK0_IN;
    volatile Uint32 CFG_XREF_CLK0_OEN;
    volatile Uint32 CFG_XREF_CLK0_OUT;
    volatile Uint32 CFG_XREF_CLK1_IN;
    volatile Uint32 CFG_XREF_CLK1_OEN;
    volatile Uint32 CFG_XREF_CLK1_OUT;
    volatile Uint32 CFG_XREF_CLK2_IN;
    volatile Uint32 CFG_XREF_CLK2_OEN;
    volatile Uint32 CFG_XREF_CLK2_OUT;
    volatile Uint32 CFG_XREF_CLK3_IN;
    volatile Uint32 CFG_XREF_CLK3_OEN;
    volatile Uint32 CFG_XREF_CLK3_OUT;
} CSL_IodelayconfigRegs;


/**************************************************************************
* Register Macros
**************************************************************************/

/* IP Revision Register */
#define CSL_IODELAYCONFIG_IP_REVISION                           (0x0U)

/* IP Hardware Info Register */
#define CSL_IODELAYCONFIG_IP_HWINFO                             (0x4U)

/* IP Sysconfig Register */
#define CSL_IODELAYCONFIG_IP_SYSCONFIG                          (0x8U)

/* Calibration Control Register */
#define CSL_IODELAYCONFIG_CONFIG_REG_0                          (0xCU)

/* Expected Delay Register */
#define CSL_IODELAYCONFIG_CONFIG_REG_1                          (0x10U)

/* Reference Clock Period Register. */
#define CSL_IODELAYCONFIG_CONFIG_REG_2                          (0x14U)

/* coarse calibration results register */
#define CSL_IODELAYCONFIG_CONFIG_REG_3                          (0x18U)

/* fine calibration results register */
#define CSL_IODELAYCONFIG_CONFIG_REG_4                          (0x1CU)

/* Delay Select Register */
#define CSL_IODELAYCONFIG_CONFIG_REG_5                          (0x20U)

/* Calibration Wait Count Register */
#define CSL_IODELAYCONFIG_CONFIG_REG_6                          (0x24U)

/* Calibration Process Count Register */
#define CSL_IODELAYCONFIG_CONFIG_REG_7                          (0x28U)

/* Global Lock Register. */
#define CSL_IODELAYCONFIG_CONFIG_REG_8                          (0x2CU)

/* Delay Select Value in binary coded form for cfg_RMII_MHZ_50_CLK_in
 * interface */
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_IN                (0x30U)

/* Delay Select Value in binary coded form for cfg_RMII_MHZ_50_CLK_oen
 * interface */
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OEN               (0x34U)

/* Delay Select Value in binary coded form for cfg_RMII_MHZ_50_CLK_out
 * interface */
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OUT               (0x38U)

/* Delay Select Value in binary coded form for cfg_Wakeup0_in interface */
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_IN                        (0x3CU)

/* Delay Select Value in binary coded form for cfg_Wakeup0_oen interface */
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OEN                       (0x40U)

/* Delay Select Value in binary coded form for cfg_Wakeup0_out interface */
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OUT                       (0x44U)

/* Delay Select Value in binary coded form for cfg_Wakeup1_in interface */
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_IN                        (0x48U)

/* Delay Select Value in binary coded form for cfg_Wakeup1_oen interface */
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OEN                       (0x4CU)

/* Delay Select Value in binary coded form for cfg_Wakeup1_out interface */
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OUT                       (0x50U)

/* Delay Select Value in binary coded form for cfg_Wakeup2_in interface */
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_IN                        (0x54U)

/* Delay Select Value in binary coded form for cfg_Wakeup2_oen interface */
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OEN                       (0x58U)

/* Delay Select Value in binary coded form for cfg_Wakeup2_out interface */
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OUT                       (0x5CU)

/* Delay Select Value in binary coded form for cfg_Wakeup3_in interface */
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_IN                        (0x60U)

/* Delay Select Value in binary coded form for cfg_Wakeup3_oen interface */
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OEN                       (0x64U)

/* Delay Select Value in binary coded form for cfg_Wakeup3_out interface */
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OUT                       (0x68U)

/* Delay Select Value in binary coded form for cfg_dcan1_rx_in interface */
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_IN                       (0x6CU)

/* Delay Select Value in binary coded form for cfg_dcan1_rx_oen interface */
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OEN                      (0x70U)

/* Delay Select Value in binary coded form for cfg_dcan1_rx_out interface */
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OUT                      (0x74U)

/* Delay Select Value in binary coded form for cfg_dcan1_tx_in interface */
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_IN                       (0x78U)

/* Delay Select Value in binary coded form for cfg_dcan1_tx_oen interface */
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OEN                      (0x7CU)

/* Delay Select Value in binary coded form for cfg_dcan1_tx_out interface */
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OUT                      (0x80U)

/* Delay Select Value in binary coded form for cfg_dcan2_rx_in interface */
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_IN                       (0x84U)

/* Delay Select Value in binary coded form for cfg_dcan2_rx_oen interface */
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OEN                      (0x88U)

/* Delay Select Value in binary coded form for cfg_dcan2_rx_out interface */
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OUT                      (0x8CU)

/* Delay Select Value in binary coded form for cfg_dcan2_tx_in interface */
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_IN                       (0x90U)

/* Delay Select Value in binary coded form for cfg_dcan2_tx_oen interface */
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OEN                      (0x94U)

/* Delay Select Value in binary coded form for cfg_dcan2_tx_out interface */
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OUT                      (0x98U)

/* Delay Select Value in binary coded form for cfg_emu0_in interface */
#define CSL_IODELAYCONFIG_CFG_EMU0_IN                           (0x9CU)

/* Delay Select Value in binary coded form for cfg_emu0_oen interface */
#define CSL_IODELAYCONFIG_CFG_EMU0_OEN                          (0xA0U)

/* Delay Select Value in binary coded form for cfg_emu0_out interface */
#define CSL_IODELAYCONFIG_CFG_EMU0_OUT                          (0xA4U)

/* Delay Select Value in binary coded form for cfg_emu1_in interface */
#define CSL_IODELAYCONFIG_CFG_EMU1_IN                           (0xA8U)

/* Delay Select Value in binary coded form for cfg_emu1_oen interface */
#define CSL_IODELAYCONFIG_CFG_EMU1_OEN                          (0xACU)

/* Delay Select Value in binary coded form for cfg_emu1_out interface */
#define CSL_IODELAYCONFIG_CFG_EMU1_OUT                          (0xB0U)

/* Delay Select Value in binary coded form for cfg_emu2_in interface */
#define CSL_IODELAYCONFIG_CFG_EMU2_IN                           (0xB4U)

/* Delay Select Value in binary coded form for cfg_emu2_oen interface */
#define CSL_IODELAYCONFIG_CFG_EMU2_OEN                          (0xB8U)

/* Delay Select Value in binary coded form for cfg_emu2_out interface */
#define CSL_IODELAYCONFIG_CFG_EMU2_OUT                          (0xBCU)

/* Delay Select Value in binary coded form for cfg_emu3_in interface */
#define CSL_IODELAYCONFIG_CFG_EMU3_IN                           (0xC0U)

/* Delay Select Value in binary coded form for cfg_emu3_oen interface */
#define CSL_IODELAYCONFIG_CFG_EMU3_OEN                          (0xC4U)

/* Delay Select Value in binary coded form for cfg_emu3_out interface */
#define CSL_IODELAYCONFIG_CFG_EMU3_OUT                          (0xC8U)

/* Delay Select Value in binary coded form for cfg_emu4_in interface */
#define CSL_IODELAYCONFIG_CFG_EMU4_IN                           (0xCCU)

/* Delay Select Value in binary coded form for cfg_emu4_oen interface */
#define CSL_IODELAYCONFIG_CFG_EMU4_OEN                          (0xD0U)

/* Delay Select Value in binary coded form for cfg_emu4_out interface */
#define CSL_IODELAYCONFIG_CFG_EMU4_OUT                          (0xD4U)

/* Delay Select Value in binary coded form for cfg_gpio6_10_in interface */
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_IN                       (0xD8U)

/* Delay Select Value in binary coded form for cfg_gpio6_10_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OEN                      (0xDCU)

/* Delay Select Value in binary coded form for cfg_gpio6_10_out interface */
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OUT                      (0xE0U)

/* Delay Select Value in binary coded form for cfg_gpio6_11_in interface */
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_IN                       (0xE4U)

/* Delay Select Value in binary coded form for cfg_gpio6_11_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OEN                      (0xE8U)

/* Delay Select Value in binary coded form for cfg_gpio6_11_out interface */
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OUT                      (0xECU)

/* Delay Select Value in binary coded form for cfg_gpio6_14_in interface */
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_IN                       (0xF0U)

/* Delay Select Value in binary coded form for cfg_gpio6_14_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OEN                      (0xF4U)

/* Delay Select Value in binary coded form for cfg_gpio6_14_out interface */
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OUT                      (0xF8U)

/* Delay Select Value in binary coded form for cfg_gpio6_15_in interface */
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_IN                       (0xFCU)

/* Delay Select Value in binary coded form for cfg_gpio6_15_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OEN                      (0x100U)

/* Delay Select Value in binary coded form for cfg_gpio6_15_out interface */
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OUT                      (0x104U)

/* Delay Select Value in binary coded form for cfg_gpio6_16_in interface */
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_IN                       (0x108U)

/* Delay Select Value in binary coded form for cfg_gpio6_16_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OEN                      (0x10CU)

/* Delay Select Value in binary coded form for cfg_gpio6_16_out interface */
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OUT                      (0x110U)

/* Delay Select Value in binary coded form for cfg_gpmc_a0_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_IN                        (0x114U)

/* Delay Select Value in binary coded form for cfg_gpmc_a0_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OEN                       (0x118U)

/* Delay Select Value in binary coded form for cfg_gpmc_a0_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OUT                       (0x11CU)

/* Delay Select Value in binary coded form for cfg_gpmc_a10_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_IN                       (0x120U)

/* Delay Select Value in binary coded form for cfg_gpmc_a10_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OEN                      (0x124U)

/* Delay Select Value in binary coded form for cfg_gpmc_a10_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OUT                      (0x128U)

/* Delay Select Value in binary coded form for cfg_gpmc_a11_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_IN                       (0x12CU)

/* Delay Select Value in binary coded form for cfg_gpmc_a11_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OEN                      (0x130U)

/* Delay Select Value in binary coded form for cfg_gpmc_a11_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OUT                      (0x134U)

/* Delay Select Value in binary coded form for cfg_gpmc_a12_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_IN                       (0x138U)

/* Delay Select Value in binary coded form for cfg_gpmc_a12_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OEN                      (0x13CU)

/* Delay Select Value in binary coded form for cfg_gpmc_a12_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OUT                      (0x140U)

/* Delay Select Value in binary coded form for cfg_gpmc_a13_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_IN                       (0x144U)

/* Delay Select Value in binary coded form for cfg_gpmc_a13_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OEN                      (0x148U)

/* Delay Select Value in binary coded form for cfg_gpmc_a13_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OUT                      (0x14CU)

/* Delay Select Value in binary coded form for cfg_gpmc_a14_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_IN                       (0x150U)

/* Delay Select Value in binary coded form for cfg_gpmc_a14_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OEN                      (0x154U)

/* Delay Select Value in binary coded form for cfg_gpmc_a14_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OUT                      (0x158U)

/* Delay Select Value in binary coded form for cfg_gpmc_a15_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_IN                       (0x15CU)

/* Delay Select Value in binary coded form for cfg_gpmc_a15_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OEN                      (0x160U)

/* Delay Select Value in binary coded form for cfg_gpmc_a15_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OUT                      (0x164U)

/* Delay Select Value in binary coded form for cfg_gpmc_a16_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_IN                       (0x168U)

/* Delay Select Value in binary coded form for cfg_gpmc_a16_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OEN                      (0x16CU)

/* Delay Select Value in binary coded form for cfg_gpmc_a16_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OUT                      (0x170U)

/* Delay Select Value in binary coded form for cfg_gpmc_a17_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_IN                       (0x174U)

/* Delay Select Value in binary coded form for cfg_gpmc_a17_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OEN                      (0x178U)

/* Delay Select Value in binary coded form for cfg_gpmc_a17_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OUT                      (0x17CU)

/* Delay Select Value in binary coded form for cfg_gpmc_a18_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_IN                       (0x180U)

/* Delay Select Value in binary coded form for cfg_gpmc_a18_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OEN                      (0x184U)

/* Delay Select Value in binary coded form for cfg_gpmc_a18_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OUT                      (0x188U)

/* Delay Select Value in binary coded form for cfg_gpmc_a19_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_IN                       (0x18CU)

/* Delay Select Value in binary coded form for cfg_gpmc_a19_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OEN                      (0x190U)

/* Delay Select Value in binary coded form for cfg_gpmc_a19_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OUT                      (0x194U)

/* Delay Select Value in binary coded form for cfg_gpmc_a1_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_IN                        (0x198U)

/* Delay Select Value in binary coded form for cfg_gpmc_a1_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OEN                       (0x19CU)

/* Delay Select Value in binary coded form for cfg_gpmc_a1_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OUT                       (0x1A0U)

/* Delay Select Value in binary coded form for cfg_gpmc_a20_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_IN                       (0x1A4U)

/* Delay Select Value in binary coded form for cfg_gpmc_a20_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OEN                      (0x1A8U)

/* Delay Select Value in binary coded form for cfg_gpmc_a20_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OUT                      (0x1ACU)

/* Delay Select Value in binary coded form for cfg_gpmc_a21_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_IN                       (0x1B0U)

/* Delay Select Value in binary coded form for cfg_gpmc_a21_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OEN                      (0x1B4U)

/* Delay Select Value in binary coded form for cfg_gpmc_a21_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OUT                      (0x1B8U)

/* Delay Select Value in binary coded form for cfg_gpmc_a22_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_IN                       (0x1BCU)

/* Delay Select Value in binary coded form for cfg_gpmc_a22_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OEN                      (0x1C0U)

/* Delay Select Value in binary coded form for cfg_gpmc_a22_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OUT                      (0x1C4U)

/* Delay Select Value in binary coded form for cfg_gpmc_a23_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_IN                       (0x1C8U)

/* Delay Select Value in binary coded form for cfg_gpmc_a23_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OEN                      (0x1CCU)

/* Delay Select Value in binary coded form for cfg_gpmc_a23_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OUT                      (0x1D0U)

/* Delay Select Value in binary coded form for cfg_gpmc_a24_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_IN                       (0x1D4U)

/* Delay Select Value in binary coded form for cfg_gpmc_a24_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OEN                      (0x1D8U)

/* Delay Select Value in binary coded form for cfg_gpmc_a24_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OUT                      (0x1DCU)

/* Delay Select Value in binary coded form for cfg_gpmc_a25_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_IN                       (0x1E0U)

/* Delay Select Value in binary coded form for cfg_gpmc_a25_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OEN                      (0x1E4U)

/* Delay Select Value in binary coded form for cfg_gpmc_a25_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OUT                      (0x1E8U)

/* Delay Select Value in binary coded form for cfg_gpmc_a26_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_IN                       (0x1ECU)

/* Delay Select Value in binary coded form for cfg_gpmc_a26_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OEN                      (0x1F0U)

/* Delay Select Value in binary coded form for cfg_gpmc_a26_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OUT                      (0x1F4U)

/* Delay Select Value in binary coded form for cfg_gpmc_a27_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_IN                       (0x1F8U)

/* Delay Select Value in binary coded form for cfg_gpmc_a27_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OEN                      (0x1FCU)

/* Delay Select Value in binary coded form for cfg_gpmc_a27_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OUT                      (0x200U)

/* Delay Select Value in binary coded form for cfg_gpmc_a2_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_IN                        (0x204U)

/* Delay Select Value in binary coded form for cfg_gpmc_a2_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OEN                       (0x208U)

/* Delay Select Value in binary coded form for cfg_gpmc_a2_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OUT                       (0x20CU)

/* Delay Select Value in binary coded form for cfg_gpmc_a3_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_IN                        (0x210U)

/* Delay Select Value in binary coded form for cfg_gpmc_a3_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OEN                       (0x214U)

/* Delay Select Value in binary coded form for cfg_gpmc_a3_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OUT                       (0x218U)

/* Delay Select Value in binary coded form for cfg_gpmc_a4_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_IN                        (0x21CU)

/* Delay Select Value in binary coded form for cfg_gpmc_a4_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OEN                       (0x220U)

/* Delay Select Value in binary coded form for cfg_gpmc_a4_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OUT                       (0x224U)

/* Delay Select Value in binary coded form for cfg_gpmc_a5_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_IN                        (0x228U)

/* Delay Select Value in binary coded form for cfg_gpmc_a5_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OEN                       (0x22CU)

/* Delay Select Value in binary coded form for cfg_gpmc_a5_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OUT                       (0x230U)

/* Delay Select Value in binary coded form for cfg_gpmc_a6_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_IN                        (0x234U)

/* Delay Select Value in binary coded form for cfg_gpmc_a6_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OEN                       (0x238U)

/* Delay Select Value in binary coded form for cfg_gpmc_a6_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OUT                       (0x23CU)

/* Delay Select Value in binary coded form for cfg_gpmc_a7_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_IN                        (0x240U)

/* Delay Select Value in binary coded form for cfg_gpmc_a7_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OEN                       (0x244U)

/* Delay Select Value in binary coded form for cfg_gpmc_a7_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OUT                       (0x248U)

/* Delay Select Value in binary coded form for cfg_gpmc_a8_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_IN                        (0x24CU)

/* Delay Select Value in binary coded form for cfg_gpmc_a8_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OEN                       (0x250U)

/* Delay Select Value in binary coded form for cfg_gpmc_a8_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OUT                       (0x254U)

/* Delay Select Value in binary coded form for cfg_gpmc_a9_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_IN                        (0x258U)

/* Delay Select Value in binary coded form for cfg_gpmc_a9_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OEN                       (0x25CU)

/* Delay Select Value in binary coded form for cfg_gpmc_a9_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OUT                       (0x260U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad0_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_IN                       (0x264U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad0_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OEN                      (0x268U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad0_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OUT                      (0x26CU)

/* Delay Select Value in binary coded form for cfg_gpmc_ad10_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_IN                      (0x270U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad10_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OEN                     (0x274U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad10_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OUT                     (0x278U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad11_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_IN                      (0x27CU)

/* Delay Select Value in binary coded form for cfg_gpmc_ad11_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OEN                     (0x280U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad11_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OUT                     (0x284U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad12_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_IN                      (0x288U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad12_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OEN                     (0x28CU)

/* Delay Select Value in binary coded form for cfg_gpmc_ad12_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OUT                     (0x290U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad13_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_IN                      (0x294U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad13_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OEN                     (0x298U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad13_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OUT                     (0x29CU)

/* Delay Select Value in binary coded form for cfg_gpmc_ad14_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_IN                      (0x2A0U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad14_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OEN                     (0x2A4U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad14_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OUT                     (0x2A8U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad15_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_IN                      (0x2ACU)

/* Delay Select Value in binary coded form for cfg_gpmc_ad15_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OEN                     (0x2B0U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad15_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OUT                     (0x2B4U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad1_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_IN                       (0x2B8U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad1_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OEN                      (0x2BCU)

/* Delay Select Value in binary coded form for cfg_gpmc_ad1_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OUT                      (0x2C0U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad2_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_IN                       (0x2C4U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad2_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OEN                      (0x2C8U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad2_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OUT                      (0x2CCU)

/* Delay Select Value in binary coded form for cfg_gpmc_ad3_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_IN                       (0x2D0U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad3_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OEN                      (0x2D4U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad3_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OUT                      (0x2D8U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad4_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_IN                       (0x2DCU)

/* Delay Select Value in binary coded form for cfg_gpmc_ad4_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OEN                      (0x2E0U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad4_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OUT                      (0x2E4U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad5_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_IN                       (0x2E8U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad5_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OEN                      (0x2ECU)

/* Delay Select Value in binary coded form for cfg_gpmc_ad5_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OUT                      (0x2F0U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad6_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_IN                       (0x2F4U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad6_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OEN                      (0x2F8U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad6_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OUT                      (0x2FCU)

/* Delay Select Value in binary coded form for cfg_gpmc_ad7_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_IN                       (0x300U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad7_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OEN                      (0x304U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad7_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OUT                      (0x308U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad8_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_IN                       (0x30CU)

/* Delay Select Value in binary coded form for cfg_gpmc_ad8_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OEN                      (0x310U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad8_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OUT                      (0x314U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad9_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_IN                       (0x318U)

/* Delay Select Value in binary coded form for cfg_gpmc_ad9_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OEN                      (0x31CU)

/* Delay Select Value in binary coded form for cfg_gpmc_ad9_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OUT                      (0x320U)

/* Delay Select Value in binary coded form for cfg_gpmc_advn_ale_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_IN                  (0x324U)

/* Delay Select Value in binary coded form for cfg_gpmc_advn_ale_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OEN                 (0x328U)

/* Delay Select Value in binary coded form for cfg_gpmc_advn_ale_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OUT                 (0x32CU)

/* Delay Select Value in binary coded form for cfg_gpmc_ben0_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_IN                      (0x330U)

/* Delay Select Value in binary coded form for cfg_gpmc_ben0_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OEN                     (0x334U)

/* Delay Select Value in binary coded form for cfg_gpmc_ben0_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OUT                     (0x338U)

/* Delay Select Value in binary coded form for cfg_gpmc_ben1_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_IN                      (0x33CU)

/* Delay Select Value in binary coded form for cfg_gpmc_ben1_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OEN                     (0x340U)

/* Delay Select Value in binary coded form for cfg_gpmc_ben1_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OUT                     (0x344U)

/* Delay Select Value in binary coded form for cfg_gpmc_clk_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_IN                       (0x348U)

/* Delay Select Value in binary coded form for cfg_gpmc_clk_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OEN                      (0x34CU)

/* Delay Select Value in binary coded form for cfg_gpmc_clk_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OUT                      (0x350U)

/* Delay Select Value in binary coded form for cfg_gpmc_cs0_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_IN                       (0x354U)

/* Delay Select Value in binary coded form for cfg_gpmc_cs0_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OEN                      (0x358U)

/* Delay Select Value in binary coded form for cfg_gpmc_cs0_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OUT                      (0x35CU)

/* Delay Select Value in binary coded form for cfg_gpmc_cs1_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_IN                       (0x360U)

/* Delay Select Value in binary coded form for cfg_gpmc_cs1_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OEN                      (0x364U)

/* Delay Select Value in binary coded form for cfg_gpmc_cs1_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OUT                      (0x368U)

/* Delay Select Value in binary coded form for cfg_gpmc_cs2_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_IN                       (0x36CU)

/* Delay Select Value in binary coded form for cfg_gpmc_cs2_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OEN                      (0x370U)

/* Delay Select Value in binary coded form for cfg_gpmc_cs2_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OUT                      (0x374U)

/* Delay Select Value in binary coded form for cfg_gpmc_cs3_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_IN                       (0x378U)

/* Delay Select Value in binary coded form for cfg_gpmc_cs3_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OEN                      (0x37CU)

/* Delay Select Value in binary coded form for cfg_gpmc_cs3_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OUT                      (0x380U)

/* Delay Select Value in binary coded form for cfg_gpmc_oen_ren_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_IN                   (0x384U)

/* Delay Select Value in binary coded form for cfg_gpmc_oen_ren_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OEN                  (0x388U)

/* Delay Select Value in binary coded form for cfg_gpmc_oen_ren_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OUT                  (0x38CU)

/* Delay Select Value in binary coded form for cfg_gpmc_wait0_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_IN                     (0x390U)

/* Delay Select Value in binary coded form for cfg_gpmc_wait0_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OEN                    (0x394U)

/* Delay Select Value in binary coded form for cfg_gpmc_wait0_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OUT                    (0x398U)

/* Delay Select Value in binary coded form for cfg_gpmc_wen_in interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_IN                       (0x39CU)

/* Delay Select Value in binary coded form for cfg_gpmc_wen_oen interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OEN                      (0x3A0U)

/* Delay Select Value in binary coded form for cfg_gpmc_wen_out interface */
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OUT                      (0x3A4U)

/* Delay Select Value in binary coded form for cfg_mcasp1_aclkr_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_IN                   (0x3A8U)

/* Delay Select Value in binary coded form for cfg_mcasp1_aclkr_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OEN                  (0x3ACU)

/* Delay Select Value in binary coded form for cfg_mcasp1_aclkr_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OUT                  (0x3B0U)

/* Delay Select Value in binary coded form for cfg_mcasp1_aclkx_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_IN                   (0x3B4U)

/* Delay Select Value in binary coded form for cfg_mcasp1_aclkx_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OEN                  (0x3B8U)

/* Delay Select Value in binary coded form for cfg_mcasp1_aclkx_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OUT                  (0x3BCU)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr0_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_IN                    (0x3C0U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr0_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OEN                   (0x3C4U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr0_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OUT                   (0x3C8U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr10_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_IN                   (0x3CCU)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr10_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OEN                  (0x3D0U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr10_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OUT                  (0x3D4U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr11_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_IN                   (0x3D8U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr11_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OEN                  (0x3DCU)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr11_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OUT                  (0x3E0U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr12_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_IN                   (0x3E4U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr12_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OEN                  (0x3E8U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr12_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OUT                  (0x3ECU)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr13_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_IN                   (0x3F0U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr13_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OEN                  (0x3F4U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr13_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OUT                  (0x3F8U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr14_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_IN                   (0x3FCU)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr14_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OEN                  (0x400U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr14_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OUT                  (0x404U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr15_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_IN                   (0x408U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr15_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OEN                  (0x40CU)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr15_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OUT                  (0x410U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr1_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_IN                    (0x414U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr1_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OEN                   (0x418U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr1_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OUT                   (0x41CU)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr2_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_IN                    (0x420U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr2_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OEN                   (0x424U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr2_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OUT                   (0x428U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr3_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_IN                    (0x42CU)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr3_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OEN                   (0x430U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr3_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OUT                   (0x434U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr4_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_IN                    (0x438U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr4_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OEN                   (0x43CU)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr4_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OUT                   (0x440U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr5_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_IN                    (0x444U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr5_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OEN                   (0x448U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr5_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OUT                   (0x44CU)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr6_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_IN                    (0x450U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr6_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OEN                   (0x454U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr6_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OUT                   (0x458U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr7_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_IN                    (0x45CU)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr7_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OEN                   (0x460U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr7_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OUT                   (0x464U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr8_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_IN                    (0x468U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr8_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OEN                   (0x46CU)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr8_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OUT                   (0x470U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr9_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_IN                    (0x474U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr9_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OEN                   (0x478U)

/* Delay Select Value in binary coded form for cfg_mcasp1_axr9_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OUT                   (0x47CU)

/* Delay Select Value in binary coded form for cfg_mcasp1_fsr_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_IN                     (0x480U)

/* Delay Select Value in binary coded form for cfg_mcasp1_fsr_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OEN                    (0x484U)

/* Delay Select Value in binary coded form for cfg_mcasp1_fsr_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OUT                    (0x488U)

/* Delay Select Value in binary coded form for cfg_mcasp1_fsx_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_IN                     (0x48CU)

/* Delay Select Value in binary coded form for cfg_mcasp1_fsx_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OEN                    (0x490U)

/* Delay Select Value in binary coded form for cfg_mcasp1_fsx_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OUT                    (0x494U)

/* Delay Select Value in binary coded form for cfg_mcasp2_aclkr_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_IN                   (0x498U)

/* Delay Select Value in binary coded form for cfg_mcasp2_aclkr_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OEN                  (0x49CU)

/* Delay Select Value in binary coded form for cfg_mcasp2_aclkr_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OUT                  (0x4A0U)

/* Delay Select Value in binary coded form for cfg_mcasp2_aclkx_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_IN                   (0x4A4U)

/* Delay Select Value in binary coded form for cfg_mcasp2_aclkx_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OEN                  (0x4A8U)

/* Delay Select Value in binary coded form for cfg_mcasp2_aclkx_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OUT                  (0x4ACU)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr0_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_IN                    (0x4B0U)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr0_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OEN                   (0x4B4U)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr0_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OUT                   (0x4B8U)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr1_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_IN                    (0x4BCU)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr1_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OEN                   (0x4C0U)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr1_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OUT                   (0x4C4U)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr2_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_IN                    (0x4C8U)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr2_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OEN                   (0x4CCU)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr2_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OUT                   (0x4D0U)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr3_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_IN                    (0x4D4U)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr3_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OEN                   (0x4D8U)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr3_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OUT                   (0x4DCU)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr4_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_IN                    (0x4E0U)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr4_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OEN                   (0x4E4U)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr4_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OUT                   (0x4E8U)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr5_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_IN                    (0x4ECU)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr5_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OEN                   (0x4F0U)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr5_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OUT                   (0x4F4U)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr6_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_IN                    (0x4F8U)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr6_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OEN                   (0x4FCU)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr6_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OUT                   (0x500U)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr7_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_IN                    (0x504U)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr7_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OEN                   (0x508U)

/* Delay Select Value in binary coded form for cfg_mcasp2_axr7_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OUT                   (0x50CU)

/* Delay Select Value in binary coded form for cfg_mcasp2_fsr_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_IN                     (0x510U)

/* Delay Select Value in binary coded form for cfg_mcasp2_fsr_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OEN                    (0x514U)

/* Delay Select Value in binary coded form for cfg_mcasp2_fsr_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OUT                    (0x518U)

/* Delay Select Value in binary coded form for cfg_mcasp2_fsx_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_IN                     (0x51CU)

/* Delay Select Value in binary coded form for cfg_mcasp2_fsx_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OEN                    (0x520U)

/* Delay Select Value in binary coded form for cfg_mcasp2_fsx_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OUT                    (0x524U)

/* Delay Select Value in binary coded form for cfg_mcasp3_aclkx_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_IN                   (0x528U)

/* Delay Select Value in binary coded form for cfg_mcasp3_aclkx_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OEN                  (0x52CU)

/* Delay Select Value in binary coded form for cfg_mcasp3_aclkx_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OUT                  (0x530U)

/* Delay Select Value in binary coded form for cfg_mcasp3_axr0_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_IN                    (0x534U)

/* Delay Select Value in binary coded form for cfg_mcasp3_axr0_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OEN                   (0x538U)

/* Delay Select Value in binary coded form for cfg_mcasp3_axr0_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OUT                   (0x53CU)

/* Delay Select Value in binary coded form for cfg_mcasp3_axr1_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_IN                    (0x540U)

/* Delay Select Value in binary coded form for cfg_mcasp3_axr1_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OEN                   (0x544U)

/* Delay Select Value in binary coded form for cfg_mcasp3_axr1_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OUT                   (0x548U)

/* Delay Select Value in binary coded form for cfg_mcasp3_fsx_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_IN                     (0x54CU)

/* Delay Select Value in binary coded form for cfg_mcasp3_fsx_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OEN                    (0x550U)

/* Delay Select Value in binary coded form for cfg_mcasp3_fsx_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OUT                    (0x554U)

/* Delay Select Value in binary coded form for cfg_mcasp4_aclkx_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_IN                   (0x558U)

/* Delay Select Value in binary coded form for cfg_mcasp4_aclkx_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OEN                  (0x55CU)

/* Delay Select Value in binary coded form for cfg_mcasp4_aclkx_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OUT                  (0x560U)

/* Delay Select Value in binary coded form for cfg_mcasp4_axr0_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_IN                    (0x564U)

/* Delay Select Value in binary coded form for cfg_mcasp4_axr0_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OEN                   (0x568U)

/* Delay Select Value in binary coded form for cfg_mcasp4_axr0_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OUT                   (0x56CU)

/* Delay Select Value in binary coded form for cfg_mcasp4_axr1_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_IN                    (0x570U)

/* Delay Select Value in binary coded form for cfg_mcasp4_axr1_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OEN                   (0x574U)

/* Delay Select Value in binary coded form for cfg_mcasp4_axr1_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OUT                   (0x578U)

/* Delay Select Value in binary coded form for cfg_mcasp4_fsx_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_IN                     (0x57CU)

/* Delay Select Value in binary coded form for cfg_mcasp4_fsx_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OEN                    (0x580U)

/* Delay Select Value in binary coded form for cfg_mcasp4_fsx_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OUT                    (0x584U)

/* Delay Select Value in binary coded form for cfg_mcasp5_aclkx_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_IN                   (0x588U)

/* Delay Select Value in binary coded form for cfg_mcasp5_aclkx_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OEN                  (0x58CU)

/* Delay Select Value in binary coded form for cfg_mcasp5_aclkx_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OUT                  (0x590U)

/* Delay Select Value in binary coded form for cfg_mcasp5_axr0_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_IN                    (0x594U)

/* Delay Select Value in binary coded form for cfg_mcasp5_axr0_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OEN                   (0x598U)

/* Delay Select Value in binary coded form for cfg_mcasp5_axr0_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OUT                   (0x59CU)

/* Delay Select Value in binary coded form for cfg_mcasp5_axr1_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_IN                    (0x5A0U)

/* Delay Select Value in binary coded form for cfg_mcasp5_axr1_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OEN                   (0x5A4U)

/* Delay Select Value in binary coded form for cfg_mcasp5_axr1_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OUT                   (0x5A8U)

/* Delay Select Value in binary coded form for cfg_mcasp5_fsx_in interface */
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_IN                     (0x5ACU)

/* Delay Select Value in binary coded form for cfg_mcasp5_fsx_oen interface */
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OEN                    (0x5B0U)

/* Delay Select Value in binary coded form for cfg_mcasp5_fsx_out interface */
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OUT                    (0x5B4U)

/* Delay Select Value in binary coded form for cfg_mdio_d_in interface */
#define CSL_IODELAYCONFIG_CFG_MDIO_D_IN                         (0x5B8U)

/* Delay Select Value in binary coded form for cfg_mdio_d_oen interface */
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OEN                        (0x5BCU)

/* Delay Select Value in binary coded form for cfg_mdio_d_out interface */
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OUT                        (0x5C0U)

/* Delay Select Value in binary coded form for cfg_mdio_mclk_in interface */
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_IN                      (0x5C4U)

/* Delay Select Value in binary coded form for cfg_mdio_mclk_oen interface */
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OEN                     (0x5C8U)

/* Delay Select Value in binary coded form for cfg_mdio_mclk_out interface */
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OUT                     (0x5CCU)

/* Delay Select Value in binary coded form for cfg_mlbp_clk_n_in interface */
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_IN                     (0x5D0U)

/* Delay Select Value in binary coded form for cfg_mlbp_clk_n_oen interface */
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OEN                    (0x5D4U)

/* Delay Select Value in binary coded form for cfg_mlbp_clk_n_out interface */
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OUT                    (0x5D8U)

/* Delay Select Value in binary coded form for cfg_mlbp_clk_p_in interface */
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_IN                     (0x5DCU)

/* Delay Select Value in binary coded form for cfg_mlbp_clk_p_oen interface */
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OEN                    (0x5E0U)

/* Delay Select Value in binary coded form for cfg_mlbp_clk_p_out interface */
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OUT                    (0x5E4U)

/* Delay Select Value in binary coded form for cfg_mlbp_dat_n_in interface */
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_IN                     (0x5E8U)

/* Delay Select Value in binary coded form for cfg_mlbp_dat_n_oen interface */
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OEN                    (0x5ECU)

/* Delay Select Value in binary coded form for cfg_mlbp_dat_n_out interface */
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OUT                    (0x5F0U)

/* Delay Select Value in binary coded form for cfg_mlbp_dat_p_in interface */
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_IN                     (0x5F4U)

/* Delay Select Value in binary coded form for cfg_mlbp_dat_p_oen interface */
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OEN                    (0x5F8U)

/* Delay Select Value in binary coded form for cfg_mlbp_dat_p_out interface */
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OUT                    (0x5FCU)

/* Delay Select Value in binary coded form for cfg_mlbp_sig_n_in interface */
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_IN                     (0x600U)

/* Delay Select Value in binary coded form for cfg_mlbp_sig_n_oen interface */
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OEN                    (0x604U)

/* Delay Select Value in binary coded form for cfg_mlbp_sig_n_out interface */
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OUT                    (0x608U)

/* Delay Select Value in binary coded form for cfg_mlbp_sig_p_in interface */
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_IN                     (0x60CU)

/* Delay Select Value in binary coded form for cfg_mlbp_sig_p_oen interface */
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OEN                    (0x610U)

/* Delay Select Value in binary coded form for cfg_mlbp_sig_p_out interface */
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OUT                    (0x614U)

/* Delay Select Value in binary coded form for cfg_mmc1_clk_in interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_IN                       (0x618U)

/* Delay Select Value in binary coded form for cfg_mmc1_clk_oen interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OEN                      (0x61CU)

/* Delay Select Value in binary coded form for cfg_mmc1_clk_out interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OUT                      (0x620U)

/* Delay Select Value in binary coded form for cfg_mmc1_cmd_in interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_IN                       (0x624U)

/* Delay Select Value in binary coded form for cfg_mmc1_cmd_oen interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OEN                      (0x628U)

/* Delay Select Value in binary coded form for cfg_mmc1_cmd_out interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OUT                      (0x62CU)

/* Delay Select Value in binary coded form for cfg_mmc1_dat0_in interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_IN                      (0x630U)

/* Delay Select Value in binary coded form for cfg_mmc1_dat0_oen interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OEN                     (0x634U)

/* Delay Select Value in binary coded form for cfg_mmc1_dat0_out interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OUT                     (0x638U)

/* Delay Select Value in binary coded form for cfg_mmc1_dat1_in interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_IN                      (0x63CU)

/* Delay Select Value in binary coded form for cfg_mmc1_dat1_oen interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OEN                     (0x640U)

/* Delay Select Value in binary coded form for cfg_mmc1_dat1_out interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OUT                     (0x644U)

/* Delay Select Value in binary coded form for cfg_mmc1_dat2_in interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_IN                      (0x648U)

/* Delay Select Value in binary coded form for cfg_mmc1_dat2_oen interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OEN                     (0x64CU)

/* Delay Select Value in binary coded form for cfg_mmc1_dat2_out interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OUT                     (0x650U)

/* Delay Select Value in binary coded form for cfg_mmc1_dat3_in interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_IN                      (0x654U)

/* Delay Select Value in binary coded form for cfg_mmc1_dat3_oen interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OEN                     (0x658U)

/* Delay Select Value in binary coded form for cfg_mmc1_dat3_out interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OUT                     (0x65CU)

/* Delay Select Value in binary coded form for cfg_mmc1_sdcd_in interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_IN                      (0x660U)

/* Delay Select Value in binary coded form for cfg_mmc1_sdcd_oen interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OEN                     (0x664U)

/* Delay Select Value in binary coded form for cfg_mmc1_sdcd_out interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OUT                     (0x668U)

/* Delay Select Value in binary coded form for cfg_mmc1_sdwp_in interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_IN                      (0x66CU)

/* Delay Select Value in binary coded form for cfg_mmc1_sdwp_oen interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OEN                     (0x670U)

/* Delay Select Value in binary coded form for cfg_mmc1_sdwp_out interface */
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OUT                     (0x674U)

/* Delay Select Value in binary coded form for cfg_mmc3_clk_in interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_IN                       (0x678U)

/* Delay Select Value in binary coded form for cfg_mmc3_clk_oen interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OEN                      (0x67CU)

/* Delay Select Value in binary coded form for cfg_mmc3_clk_out interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OUT                      (0x680U)

/* Delay Select Value in binary coded form for cfg_mmc3_cmd_in interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_IN                       (0x684U)

/* Delay Select Value in binary coded form for cfg_mmc3_cmd_oen interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OEN                      (0x688U)

/* Delay Select Value in binary coded form for cfg_mmc3_cmd_out interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OUT                      (0x68CU)

/* Delay Select Value in binary coded form for cfg_mmc3_dat0_in interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_IN                      (0x690U)

/* Delay Select Value in binary coded form for cfg_mmc3_dat0_oen interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OEN                     (0x694U)

/* Delay Select Value in binary coded form for cfg_mmc3_dat0_out interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OUT                     (0x698U)

/* Delay Select Value in binary coded form for cfg_mmc3_dat1_in interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_IN                      (0x69CU)

/* Delay Select Value in binary coded form for cfg_mmc3_dat1_oen interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OEN                     (0x6A0U)

/* Delay Select Value in binary coded form for cfg_mmc3_dat1_out interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OUT                     (0x6A4U)

/* Delay Select Value in binary coded form for cfg_mmc3_dat2_in interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_IN                      (0x6A8U)

/* Delay Select Value in binary coded form for cfg_mmc3_dat2_oen interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OEN                     (0x6ACU)

/* Delay Select Value in binary coded form for cfg_mmc3_dat2_out interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OUT                     (0x6B0U)

/* Delay Select Value in binary coded form for cfg_mmc3_dat3_in interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_IN                      (0x6B4U)

/* Delay Select Value in binary coded form for cfg_mmc3_dat3_oen interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OEN                     (0x6B8U)

/* Delay Select Value in binary coded form for cfg_mmc3_dat3_out interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OUT                     (0x6BCU)

/* Delay Select Value in binary coded form for cfg_mmc3_dat4_in interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_IN                      (0x6C0U)

/* Delay Select Value in binary coded form for cfg_mmc3_dat4_oen interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OEN                     (0x6C4U)

/* Delay Select Value in binary coded form for cfg_mmc3_dat4_out interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OUT                     (0x6C8U)

/* Delay Select Value in binary coded form for cfg_mmc3_dat5_in interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_IN                      (0x6CCU)

/* Delay Select Value in binary coded form for cfg_mmc3_dat5_oen interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OEN                     (0x6D0U)

/* Delay Select Value in binary coded form for cfg_mmc3_dat5_out interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OUT                     (0x6D4U)

/* Delay Select Value in binary coded form for cfg_mmc3_dat6_in interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_IN                      (0x6D8U)

/* Delay Select Value in binary coded form for cfg_mmc3_dat6_oen interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OEN                     (0x6DCU)

/* Delay Select Value in binary coded form for cfg_mmc3_dat6_out interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OUT                     (0x6E0U)

/* Delay Select Value in binary coded form for cfg_mmc3_dat7_in interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_IN                      (0x6E4U)

/* Delay Select Value in binary coded form for cfg_mmc3_dat7_oen interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OEN                     (0x6E8U)

/* Delay Select Value in binary coded form for cfg_mmc3_dat7_out interface */
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OUT                     (0x6ECU)

/* Delay Select Value in binary coded form for cfg_rgmii0_rxc_in interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_IN                     (0x6F0U)

/* Delay Select Value in binary coded form for cfg_rgmii0_rxc_oen interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OEN                    (0x6F4U)

/* Delay Select Value in binary coded form for cfg_rgmii0_rxc_out interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OUT                    (0x6F8U)

/* Delay Select Value in binary coded form for cfg_rgmii0_rxctl_in interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_IN                   (0x6FCU)

/* Delay Select Value in binary coded form for cfg_rgmii0_rxctl_oen interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OEN                  (0x700U)

/* Delay Select Value in binary coded form for cfg_rgmii0_rxctl_out interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OUT                  (0x704U)

/* Delay Select Value in binary coded form for cfg_rgmii0_rxd0_in interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_IN                    (0x708U)

/* Delay Select Value in binary coded form for cfg_rgmii0_rxd0_oen interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OEN                   (0x70CU)

/* Delay Select Value in binary coded form for cfg_rgmii0_rxd0_out interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OUT                   (0x710U)

/* Delay Select Value in binary coded form for cfg_rgmii0_rxd1_in interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_IN                    (0x714U)

/* Delay Select Value in binary coded form for cfg_rgmii0_rxd1_oen interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OEN                   (0x718U)

/* Delay Select Value in binary coded form for cfg_rgmii0_rxd1_out interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OUT                   (0x71CU)

/* Delay Select Value in binary coded form for cfg_rgmii0_rxd2_in interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_IN                    (0x720U)

/* Delay Select Value in binary coded form for cfg_rgmii0_rxd2_oen interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OEN                   (0x724U)

/* Delay Select Value in binary coded form for cfg_rgmii0_rxd2_out interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OUT                   (0x728U)

/* Delay Select Value in binary coded form for cfg_rgmii0_rxd3_in interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_IN                    (0x72CU)

/* Delay Select Value in binary coded form for cfg_rgmii0_rxd3_oen interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OEN                   (0x730U)

/* Delay Select Value in binary coded form for cfg_rgmii0_rxd3_out interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OUT                   (0x734U)

/* Delay Select Value in binary coded form for cfg_rgmii0_txc_in interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_IN                     (0x738U)

/* Delay Select Value in binary coded form for cfg_rgmii0_txc_oen interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OEN                    (0x73CU)

/* Delay Select Value in binary coded form for cfg_rgmii0_txc_out interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OUT                    (0x740U)

/* Delay Select Value in binary coded form for cfg_rgmii0_txctl_in interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_IN                   (0x744U)

/* Delay Select Value in binary coded form for cfg_rgmii0_txctl_oen interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OEN                  (0x748U)

/* Delay Select Value in binary coded form for cfg_rgmii0_txctl_out interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OUT                  (0x74CU)

/* Delay Select Value in binary coded form for cfg_rgmii0_txd0_in interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_IN                    (0x750U)

/* Delay Select Value in binary coded form for cfg_rgmii0_txd0_oen interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OEN                   (0x754U)

/* Delay Select Value in binary coded form for cfg_rgmii0_txd0_out interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OUT                   (0x758U)

/* Delay Select Value in binary coded form for cfg_rgmii0_txd1_in interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_IN                    (0x75CU)

/* Delay Select Value in binary coded form for cfg_rgmii0_txd1_oen interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OEN                   (0x760U)

/* Delay Select Value in binary coded form for cfg_rgmii0_txd1_out interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OUT                   (0x764U)

/* Delay Select Value in binary coded form for cfg_rgmii0_txd2_in interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_IN                    (0x768U)

/* Delay Select Value in binary coded form for cfg_rgmii0_txd2_oen interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OEN                   (0x76CU)

/* Delay Select Value in binary coded form for cfg_rgmii0_txd2_out interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OUT                   (0x770U)

/* Delay Select Value in binary coded form for cfg_rgmii0_txd3_in interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_IN                    (0x774U)

/* Delay Select Value in binary coded form for cfg_rgmii0_txd3_oen interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OEN                   (0x778U)

/* Delay Select Value in binary coded form for cfg_rgmii0_txd3_out interface */
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OUT                   (0x77CU)

/* Delay Select Value in binary coded form for cfg_rtck_in interface */
#define CSL_IODELAYCONFIG_CFG_RTCK_IN                           (0x780U)

/* Delay Select Value in binary coded form for cfg_rtck_oen interface */
#define CSL_IODELAYCONFIG_CFG_RTCK_OEN                          (0x784U)

/* Delay Select Value in binary coded form for cfg_rtck_out interface */
#define CSL_IODELAYCONFIG_CFG_RTCK_OUT                          (0x788U)

/* Delay Select Value in binary coded form for cfg_spi1_cs0_in interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_IN                       (0x78CU)

/* Delay Select Value in binary coded form for cfg_spi1_cs0_oen interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OEN                      (0x790U)

/* Delay Select Value in binary coded form for cfg_spi1_cs0_out interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OUT                      (0x794U)

/* Delay Select Value in binary coded form for cfg_spi1_cs1_in interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_IN                       (0x798U)

/* Delay Select Value in binary coded form for cfg_spi1_cs1_oen interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OEN                      (0x79CU)

/* Delay Select Value in binary coded form for cfg_spi1_cs1_out interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OUT                      (0x7A0U)

/* Delay Select Value in binary coded form for cfg_spi1_cs2_in interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_IN                       (0x7A4U)

/* Delay Select Value in binary coded form for cfg_spi1_cs2_oen interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OEN                      (0x7A8U)

/* Delay Select Value in binary coded form for cfg_spi1_cs2_out interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OUT                      (0x7ACU)

/* Delay Select Value in binary coded form for cfg_spi1_cs3_in interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_IN                       (0x7B0U)

/* Delay Select Value in binary coded form for cfg_spi1_cs3_oen interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OEN                      (0x7B4U)

/* Delay Select Value in binary coded form for cfg_spi1_cs3_out interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OUT                      (0x7B8U)

/* Delay Select Value in binary coded form for cfg_spi1_d0_in interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_IN                        (0x7BCU)

/* Delay Select Value in binary coded form for cfg_spi1_d0_oen interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OEN                       (0x7C0U)

/* Delay Select Value in binary coded form for cfg_spi1_d0_out interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OUT                       (0x7C4U)

/* Delay Select Value in binary coded form for cfg_spi1_d1_in interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_IN                        (0x7C8U)

/* Delay Select Value in binary coded form for cfg_spi1_d1_oen interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OEN                       (0x7CCU)

/* Delay Select Value in binary coded form for cfg_spi1_d1_out interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OUT                       (0x7D0U)

/* Delay Select Value in binary coded form for cfg_spi1_sclk_in interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_IN                      (0x7D4U)

/* Delay Select Value in binary coded form for cfg_spi1_sclk_oen interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OEN                     (0x7D8U)

/* Delay Select Value in binary coded form for cfg_spi1_sclk_out interface */
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OUT                     (0x7DCU)

/* Delay Select Value in binary coded form for cfg_spi2_cs0_in interface */
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_IN                       (0x7E0U)

/* Delay Select Value in binary coded form for cfg_spi2_cs0_oen interface */
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OEN                      (0x7E4U)

/* Delay Select Value in binary coded form for cfg_spi2_cs0_out interface */
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OUT                      (0x7E8U)

/* Delay Select Value in binary coded form for cfg_spi2_d0_in interface */
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_IN                        (0x7ECU)

/* Delay Select Value in binary coded form for cfg_spi2_d0_oen interface */
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OEN                       (0x7F0U)

/* Delay Select Value in binary coded form for cfg_spi2_d0_out interface */
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OUT                       (0x7F4U)

/* Delay Select Value in binary coded form for cfg_spi2_d1_in interface */
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_IN                        (0x7F8U)

/* Delay Select Value in binary coded form for cfg_spi2_d1_oen interface */
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OEN                       (0x7FCU)

/* Delay Select Value in binary coded form for cfg_spi2_d1_out interface */
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OUT                       (0x800U)

/* Delay Select Value in binary coded form for cfg_spi2_sclk_in interface */
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_IN                      (0x804U)

/* Delay Select Value in binary coded form for cfg_spi2_sclk_oen interface */
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OEN                     (0x808U)

/* Delay Select Value in binary coded form for cfg_spi2_sclk_out interface */
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OUT                     (0x80CU)

/* Delay Select Value in binary coded form for cfg_tdi_in interface */
#define CSL_IODELAYCONFIG_CFG_TDI_IN                            (0x810U)

/* Delay Select Value in binary coded form for cfg_tdi_oen interface */
#define CSL_IODELAYCONFIG_CFG_TDI_OEN                           (0x814U)

/* Delay Select Value in binary coded form for cfg_tdi_out interface */
#define CSL_IODELAYCONFIG_CFG_TDI_OUT                           (0x818U)

/* Delay Select Value in binary coded form for cfg_tdo_in interface */
#define CSL_IODELAYCONFIG_CFG_TDO_IN                            (0x81CU)

/* Delay Select Value in binary coded form for cfg_tdo_oen interface */
#define CSL_IODELAYCONFIG_CFG_TDO_OEN                           (0x820U)

/* Delay Select Value in binary coded form for cfg_tdo_out interface */
#define CSL_IODELAYCONFIG_CFG_TDO_OUT                           (0x824U)

/* Delay Select Value in binary coded form for cfg_tms_in interface */
#define CSL_IODELAYCONFIG_CFG_TMS_IN                            (0x828U)

/* Delay Select Value in binary coded form for cfg_tms_oen interface */
#define CSL_IODELAYCONFIG_CFG_TMS_OEN                           (0x82CU)

/* Delay Select Value in binary coded form for cfg_tms_out interface */
#define CSL_IODELAYCONFIG_CFG_TMS_OUT                           (0x830U)

/* Delay Select Value in binary coded form for cfg_trstn_in interface */
#define CSL_IODELAYCONFIG_CFG_TRSTN_IN                          (0x834U)

/* Delay Select Value in binary coded form for cfg_trstn_oen interface */
#define CSL_IODELAYCONFIG_CFG_TRSTN_OEN                         (0x838U)

/* Delay Select Value in binary coded form for cfg_trstn_out interface */
#define CSL_IODELAYCONFIG_CFG_TRSTN_OUT                         (0x83CU)

/* Delay Select Value in binary coded form for cfg_uart1_ctsn_in interface */
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_IN                     (0x840U)

/* Delay Select Value in binary coded form for cfg_uart1_ctsn_oen interface */
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OEN                    (0x844U)

/* Delay Select Value in binary coded form for cfg_uart1_ctsn_out interface */
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OUT                    (0x848U)

/* Delay Select Value in binary coded form for cfg_uart1_rtsn_in interface */
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_IN                     (0x84CU)

/* Delay Select Value in binary coded form for cfg_uart1_rtsn_oen interface */
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OEN                    (0x850U)

/* Delay Select Value in binary coded form for cfg_uart1_rtsn_out interface */
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OUT                    (0x854U)

/* Delay Select Value in binary coded form for cfg_uart1_rxd_in interface */
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_IN                      (0x858U)

/* Delay Select Value in binary coded form for cfg_uart1_rxd_oen interface */
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OEN                     (0x85CU)

/* Delay Select Value in binary coded form for cfg_uart1_rxd_out interface */
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OUT                     (0x860U)

/* Delay Select Value in binary coded form for cfg_uart1_txd_in interface */
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_IN                      (0x864U)

/* Delay Select Value in binary coded form for cfg_uart1_txd_oen interface */
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OEN                     (0x868U)

/* Delay Select Value in binary coded form for cfg_uart1_txd_out interface */
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OUT                     (0x86CU)

/* Delay Select Value in binary coded form for cfg_uart2_ctsn_in interface */
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_IN                     (0x870U)

/* Delay Select Value in binary coded form for cfg_uart2_ctsn_oen interface */
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OEN                    (0x874U)

/* Delay Select Value in binary coded form for cfg_uart2_ctsn_out interface */
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OUT                    (0x878U)

/* Delay Select Value in binary coded form for cfg_uart2_rtsn_in interface */
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_IN                     (0x87CU)

/* Delay Select Value in binary coded form for cfg_uart2_rtsn_oen interface */
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OEN                    (0x880U)

/* Delay Select Value in binary coded form for cfg_uart2_rtsn_out interface */
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OUT                    (0x884U)

/* Delay Select Value in binary coded form for cfg_uart2_rxd_in interface */
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_IN                      (0x888U)

/* Delay Select Value in binary coded form for cfg_uart2_rxd_oen interface */
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OEN                     (0x88CU)

/* Delay Select Value in binary coded form for cfg_uart2_rxd_out interface */
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OUT                     (0x890U)

/* Delay Select Value in binary coded form for cfg_uart2_txd_in interface */
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_IN                      (0x894U)

/* Delay Select Value in binary coded form for cfg_uart2_txd_oen interface */
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OEN                     (0x898U)

/* Delay Select Value in binary coded form for cfg_uart2_txd_out interface */
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OUT                     (0x89CU)

/* Delay Select Value in binary coded form for cfg_uart3_rxd_in interface */
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_IN                      (0x8A0U)

/* Delay Select Value in binary coded form for cfg_uart3_rxd_oen interface */
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OEN                     (0x8A4U)

/* Delay Select Value in binary coded form for cfg_uart3_rxd_out interface */
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OUT                     (0x8A8U)

/* Delay Select Value in binary coded form for cfg_uart3_txd_in interface */
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_IN                      (0x8ACU)

/* Delay Select Value in binary coded form for cfg_uart3_txd_oen interface */
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OEN                     (0x8B0U)

/* Delay Select Value in binary coded form for cfg_uart3_txd_out interface */
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OUT                     (0x8B4U)

/* Delay Select Value in binary coded form for cfg_usb1_drvvbus_in interface */
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_IN                   (0x8B8U)

/* Delay Select Value in binary coded form for cfg_usb1_drvvbus_oen interface */
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OEN                  (0x8BCU)

/* Delay Select Value in binary coded form for cfg_usb1_drvvbus_out interface */
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OUT                  (0x8C0U)

/* Delay Select Value in binary coded form for cfg_usb2_drvvbus_in interface */
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_IN                   (0x8C4U)

/* Delay Select Value in binary coded form for cfg_usb2_drvvbus_oen interface */
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OEN                  (0x8C8U)

/* Delay Select Value in binary coded form for cfg_usb2_drvvbus_out interface */
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OUT                  (0x8CCU)

/* Delay Select Value in binary coded form for cfg_vin1a_clk0_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_IN                     (0x8D0U)

/* Delay Select Value in binary coded form for cfg_vin1a_clk0_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OEN                    (0x8D4U)

/* Delay Select Value in binary coded form for cfg_vin1a_clk0_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OUT                    (0x8D8U)

/* Delay Select Value in binary coded form for cfg_vin1a_d0_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_IN                       (0x8DCU)

/* Delay Select Value in binary coded form for cfg_vin1a_d0_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OEN                      (0x8E0U)

/* Delay Select Value in binary coded form for cfg_vin1a_d0_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OUT                      (0x8E4U)

/* Delay Select Value in binary coded form for cfg_vin1a_d10_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_IN                      (0x8E8U)

/* Delay Select Value in binary coded form for cfg_vin1a_d10_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OEN                     (0x8ECU)

/* Delay Select Value in binary coded form for cfg_vin1a_d10_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OUT                     (0x8F0U)

/* Delay Select Value in binary coded form for cfg_vin1a_d11_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_IN                      (0x8F4U)

/* Delay Select Value in binary coded form for cfg_vin1a_d11_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OEN                     (0x8F8U)

/* Delay Select Value in binary coded form for cfg_vin1a_d11_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OUT                     (0x8FCU)

/* Delay Select Value in binary coded form for cfg_vin1a_d12_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_IN                      (0x900U)

/* Delay Select Value in binary coded form for cfg_vin1a_d12_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OEN                     (0x904U)

/* Delay Select Value in binary coded form for cfg_vin1a_d12_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OUT                     (0x908U)

/* Delay Select Value in binary coded form for cfg_vin1a_d13_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_IN                      (0x90CU)

/* Delay Select Value in binary coded form for cfg_vin1a_d13_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OEN                     (0x910U)

/* Delay Select Value in binary coded form for cfg_vin1a_d13_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OUT                     (0x914U)

/* Delay Select Value in binary coded form for cfg_vin1a_d14_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_IN                      (0x918U)

/* Delay Select Value in binary coded form for cfg_vin1a_d14_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OEN                     (0x91CU)

/* Delay Select Value in binary coded form for cfg_vin1a_d14_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OUT                     (0x920U)

/* Delay Select Value in binary coded form for cfg_vin1a_d15_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_IN                      (0x924U)

/* Delay Select Value in binary coded form for cfg_vin1a_d15_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OEN                     (0x928U)

/* Delay Select Value in binary coded form for cfg_vin1a_d15_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OUT                     (0x92CU)

/* Delay Select Value in binary coded form for cfg_vin1a_d16_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_IN                      (0x930U)

/* Delay Select Value in binary coded form for cfg_vin1a_d16_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OEN                     (0x934U)

/* Delay Select Value in binary coded form for cfg_vin1a_d16_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OUT                     (0x938U)

/* Delay Select Value in binary coded form for cfg_vin1a_d17_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_IN                      (0x93CU)

/* Delay Select Value in binary coded form for cfg_vin1a_d17_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OEN                     (0x940U)

/* Delay Select Value in binary coded form for cfg_vin1a_d17_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OUT                     (0x944U)

/* Delay Select Value in binary coded form for cfg_vin1a_d18_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_IN                      (0x948U)

/* Delay Select Value in binary coded form for cfg_vin1a_d18_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OEN                     (0x94CU)

/* Delay Select Value in binary coded form for cfg_vin1a_d18_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OUT                     (0x950U)

/* Delay Select Value in binary coded form for cfg_vin1a_d19_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_IN                      (0x954U)

/* Delay Select Value in binary coded form for cfg_vin1a_d19_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OEN                     (0x958U)

/* Delay Select Value in binary coded form for cfg_vin1a_d19_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OUT                     (0x95CU)

/* Delay Select Value in binary coded form for cfg_vin1a_d1_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_IN                       (0x960U)

/* Delay Select Value in binary coded form for cfg_vin1a_d1_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OEN                      (0x964U)

/* Delay Select Value in binary coded form for cfg_vin1a_d1_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OUT                      (0x968U)

/* Delay Select Value in binary coded form for cfg_vin1a_d20_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_IN                      (0x96CU)

/* Delay Select Value in binary coded form for cfg_vin1a_d20_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OEN                     (0x970U)

/* Delay Select Value in binary coded form for cfg_vin1a_d20_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OUT                     (0x974U)

/* Delay Select Value in binary coded form for cfg_vin1a_d21_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_IN                      (0x978U)

/* Delay Select Value in binary coded form for cfg_vin1a_d21_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OEN                     (0x97CU)

/* Delay Select Value in binary coded form for cfg_vin1a_d21_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OUT                     (0x980U)

/* Delay Select Value in binary coded form for cfg_vin1a_d22_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_IN                      (0x984U)

/* Delay Select Value in binary coded form for cfg_vin1a_d22_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OEN                     (0x988U)

/* Delay Select Value in binary coded form for cfg_vin1a_d22_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OUT                     (0x98CU)

/* Delay Select Value in binary coded form for cfg_vin1a_d23_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_IN                      (0x990U)

/* Delay Select Value in binary coded form for cfg_vin1a_d23_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OEN                     (0x994U)

/* Delay Select Value in binary coded form for cfg_vin1a_d23_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OUT                     (0x998U)

/* Delay Select Value in binary coded form for cfg_vin1a_d2_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_IN                       (0x99CU)

/* Delay Select Value in binary coded form for cfg_vin1a_d2_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OEN                      (0x9A0U)

/* Delay Select Value in binary coded form for cfg_vin1a_d2_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OUT                      (0x9A4U)

/* Delay Select Value in binary coded form for cfg_vin1a_d3_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_IN                       (0x9A8U)

/* Delay Select Value in binary coded form for cfg_vin1a_d3_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OEN                      (0x9ACU)

/* Delay Select Value in binary coded form for cfg_vin1a_d3_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OUT                      (0x9B0U)

/* Delay Select Value in binary coded form for cfg_vin1a_d4_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_IN                       (0x9B4U)

/* Delay Select Value in binary coded form for cfg_vin1a_d4_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OEN                      (0x9B8U)

/* Delay Select Value in binary coded form for cfg_vin1a_d4_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OUT                      (0x9BCU)

/* Delay Select Value in binary coded form for cfg_vin1a_d5_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_IN                       (0x9C0U)

/* Delay Select Value in binary coded form for cfg_vin1a_d5_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OEN                      (0x9C4U)

/* Delay Select Value in binary coded form for cfg_vin1a_d5_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OUT                      (0x9C8U)

/* Delay Select Value in binary coded form for cfg_vin1a_d6_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_IN                       (0x9CCU)

/* Delay Select Value in binary coded form for cfg_vin1a_d6_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OEN                      (0x9D0U)

/* Delay Select Value in binary coded form for cfg_vin1a_d6_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OUT                      (0x9D4U)

/* Delay Select Value in binary coded form for cfg_vin1a_d7_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_IN                       (0x9D8U)

/* Delay Select Value in binary coded form for cfg_vin1a_d7_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OEN                      (0x9DCU)

/* Delay Select Value in binary coded form for cfg_vin1a_d7_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OUT                      (0x9E0U)

/* Delay Select Value in binary coded form for cfg_vin1a_d8_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_IN                       (0x9E4U)

/* Delay Select Value in binary coded form for cfg_vin1a_d8_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OEN                      (0x9E8U)

/* Delay Select Value in binary coded form for cfg_vin1a_d8_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OUT                      (0x9ECU)

/* Delay Select Value in binary coded form for cfg_vin1a_d9_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_IN                       (0x9F0U)

/* Delay Select Value in binary coded form for cfg_vin1a_d9_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OEN                      (0x9F4U)

/* Delay Select Value in binary coded form for cfg_vin1a_d9_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OUT                      (0x9F8U)

/* Delay Select Value in binary coded form for cfg_vin1a_de0_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_IN                      (0x9FCU)

/* Delay Select Value in binary coded form for cfg_vin1a_de0_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OEN                     (0xA00U)

/* Delay Select Value in binary coded form for cfg_vin1a_de0_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OUT                     (0xA04U)

/* Delay Select Value in binary coded form for cfg_vin1a_fld0_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_IN                     (0xA08U)

/* Delay Select Value in binary coded form for cfg_vin1a_fld0_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OEN                    (0xA0CU)

/* Delay Select Value in binary coded form for cfg_vin1a_fld0_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OUT                    (0xA10U)

/* Delay Select Value in binary coded form for cfg_vin1a_hsync0_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_IN                   (0xA14U)

/* Delay Select Value in binary coded form for cfg_vin1a_hsync0_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OEN                  (0xA18U)

/* Delay Select Value in binary coded form for cfg_vin1a_hsync0_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OUT                  (0xA1CU)

/* Delay Select Value in binary coded form for cfg_vin1a_vsync0_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_IN                   (0xA20U)

/* Delay Select Value in binary coded form for cfg_vin1a_vsync0_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OEN                  (0xA24U)

/* Delay Select Value in binary coded form for cfg_vin1a_vsync0_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OUT                  (0xA28U)

/* Delay Select Value in binary coded form for cfg_vin1b_clk1_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_IN                     (0xA2CU)

/* Delay Select Value in binary coded form for cfg_vin1b_clk1_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OEN                    (0xA30U)

/* Delay Select Value in binary coded form for cfg_vin1b_clk1_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OUT                    (0xA34U)

/* Delay Select Value in binary coded form for cfg_vin2a_clk0_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_IN                     (0xA38U)

/* Delay Select Value in binary coded form for cfg_vin2a_clk0_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OEN                    (0xA3CU)

/* Delay Select Value in binary coded form for cfg_vin2a_clk0_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OUT                    (0xA40U)

/* Delay Select Value in binary coded form for cfg_vin2a_d0_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_IN                       (0xA44U)

/* Delay Select Value in binary coded form for cfg_vin2a_d0_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OEN                      (0xA48U)

/* Delay Select Value in binary coded form for cfg_vin2a_d0_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OUT                      (0xA4CU)

/* Delay Select Value in binary coded form for cfg_vin2a_d10_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_IN                      (0xA50U)

/* Delay Select Value in binary coded form for cfg_vin2a_d10_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OEN                     (0xA54U)

/* Delay Select Value in binary coded form for cfg_vin2a_d10_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OUT                     (0xA58U)

/* Delay Select Value in binary coded form for cfg_vin2a_d11_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_IN                      (0xA5CU)

/* Delay Select Value in binary coded form for cfg_vin2a_d11_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OEN                     (0xA60U)

/* Delay Select Value in binary coded form for cfg_vin2a_d11_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OUT                     (0xA64U)

/* Delay Select Value in binary coded form for cfg_vin2a_d12_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_IN                      (0xA68U)

/* Delay Select Value in binary coded form for cfg_vin2a_d12_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OEN                     (0xA6CU)

/* Delay Select Value in binary coded form for cfg_vin2a_d12_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OUT                     (0xA70U)

/* Delay Select Value in binary coded form for cfg_vin2a_d13_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_IN                      (0xA74U)

/* Delay Select Value in binary coded form for cfg_vin2a_d13_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OEN                     (0xA78U)

/* Delay Select Value in binary coded form for cfg_vin2a_d13_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OUT                     (0xA7CU)

/* Delay Select Value in binary coded form for cfg_vin2a_d14_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_IN                      (0xA80U)

/* Delay Select Value in binary coded form for cfg_vin2a_d14_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OEN                     (0xA84U)

/* Delay Select Value in binary coded form for cfg_vin2a_d14_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OUT                     (0xA88U)

/* Delay Select Value in binary coded form for cfg_vin2a_d15_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_IN                      (0xA8CU)

/* Delay Select Value in binary coded form for cfg_vin2a_d15_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OEN                     (0xA90U)

/* Delay Select Value in binary coded form for cfg_vin2a_d15_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OUT                     (0xA94U)

/* Delay Select Value in binary coded form for cfg_vin2a_d16_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_IN                      (0xA98U)

/* Delay Select Value in binary coded form for cfg_vin2a_d16_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OEN                     (0xA9CU)

/* Delay Select Value in binary coded form for cfg_vin2a_d16_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OUT                     (0xAA0U)

/* Delay Select Value in binary coded form for cfg_vin2a_d17_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_IN                      (0xAA4U)

/* Delay Select Value in binary coded form for cfg_vin2a_d17_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OEN                     (0xAA8U)

/* Delay Select Value in binary coded form for cfg_vin2a_d17_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OUT                     (0xAACU)

/* Delay Select Value in binary coded form for cfg_vin2a_d18_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_IN                      (0xAB0U)

/* Delay Select Value in binary coded form for cfg_vin2a_d18_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OEN                     (0xAB4U)

/* Delay Select Value in binary coded form for cfg_vin2a_d18_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OUT                     (0xAB8U)

/* Delay Select Value in binary coded form for cfg_vin2a_d19_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_IN                      (0xABCU)

/* Delay Select Value in binary coded form for cfg_vin2a_d19_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OEN                     (0xAC0U)

/* Delay Select Value in binary coded form for cfg_vin2a_d19_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OUT                     (0xAC4U)

/* Delay Select Value in binary coded form for cfg_vin2a_d1_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_IN                       (0xAC8U)

/* Delay Select Value in binary coded form for cfg_vin2a_d1_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OEN                      (0xACCU)

/* Delay Select Value in binary coded form for cfg_vin2a_d1_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OUT                      (0xAD0U)

/* Delay Select Value in binary coded form for cfg_vin2a_d20_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_IN                      (0xAD4U)

/* Delay Select Value in binary coded form for cfg_vin2a_d20_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OEN                     (0xAD8U)

/* Delay Select Value in binary coded form for cfg_vin2a_d20_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OUT                     (0xADCU)

/* Delay Select Value in binary coded form for cfg_vin2a_d21_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_IN                      (0xAE0U)

/* Delay Select Value in binary coded form for cfg_vin2a_d21_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OEN                     (0xAE4U)

/* Delay Select Value in binary coded form for cfg_vin2a_d21_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OUT                     (0xAE8U)

/* Delay Select Value in binary coded form for cfg_vin2a_d22_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_IN                      (0xAECU)

/* Delay Select Value in binary coded form for cfg_vin2a_d22_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OEN                     (0xAF0U)

/* Delay Select Value in binary coded form for cfg_vin2a_d22_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OUT                     (0xAF4U)

/* Delay Select Value in binary coded form for cfg_vin2a_d23_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_IN                      (0xAF8U)

/* Delay Select Value in binary coded form for cfg_vin2a_d23_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OEN                     (0xAFCU)

/* Delay Select Value in binary coded form for cfg_vin2a_d23_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OUT                     (0xB00U)

/* Delay Select Value in binary coded form for cfg_vin2a_d2_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_IN                       (0xB04U)

/* Delay Select Value in binary coded form for cfg_vin2a_d2_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OEN                      (0xB08U)

/* Delay Select Value in binary coded form for cfg_vin2a_d2_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OUT                      (0xB0CU)

/* Delay Select Value in binary coded form for cfg_vin2a_d3_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_IN                       (0xB10U)

/* Delay Select Value in binary coded form for cfg_vin2a_d3_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OEN                      (0xB14U)

/* Delay Select Value in binary coded form for cfg_vin2a_d3_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OUT                      (0xB18U)

/* Delay Select Value in binary coded form for cfg_vin2a_d4_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_IN                       (0xB1CU)

/* Delay Select Value in binary coded form for cfg_vin2a_d4_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OEN                      (0xB20U)

/* Delay Select Value in binary coded form for cfg_vin2a_d4_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OUT                      (0xB24U)

/* Delay Select Value in binary coded form for cfg_vin2a_d5_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_IN                       (0xB28U)

/* Delay Select Value in binary coded form for cfg_vin2a_d5_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OEN                      (0xB2CU)

/* Delay Select Value in binary coded form for cfg_vin2a_d5_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OUT                      (0xB30U)

/* Delay Select Value in binary coded form for cfg_vin2a_d6_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_IN                       (0xB34U)

/* Delay Select Value in binary coded form for cfg_vin2a_d6_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OEN                      (0xB38U)

/* Delay Select Value in binary coded form for cfg_vin2a_d6_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OUT                      (0xB3CU)

/* Delay Select Value in binary coded form for cfg_vin2a_d7_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_IN                       (0xB40U)

/* Delay Select Value in binary coded form for cfg_vin2a_d7_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OEN                      (0xB44U)

/* Delay Select Value in binary coded form for cfg_vin2a_d7_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OUT                      (0xB48U)

/* Delay Select Value in binary coded form for cfg_vin2a_d8_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_IN                       (0xB4CU)

/* Delay Select Value in binary coded form for cfg_vin2a_d8_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OEN                      (0xB50U)

/* Delay Select Value in binary coded form for cfg_vin2a_d8_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OUT                      (0xB54U)

/* Delay Select Value in binary coded form for cfg_vin2a_d9_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_IN                       (0xB58U)

/* Delay Select Value in binary coded form for cfg_vin2a_d9_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OEN                      (0xB5CU)

/* Delay Select Value in binary coded form for cfg_vin2a_d9_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OUT                      (0xB60U)

/* Delay Select Value in binary coded form for cfg_vin2a_de0_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_IN                      (0xB64U)

/* Delay Select Value in binary coded form for cfg_vin2a_de0_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OEN                     (0xB68U)

/* Delay Select Value in binary coded form for cfg_vin2a_de0_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OUT                     (0xB6CU)

/* Delay Select Value in binary coded form for cfg_vin2a_fld0_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_IN                     (0xB70U)

/* Delay Select Value in binary coded form for cfg_vin2a_fld0_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OEN                    (0xB74U)

/* Delay Select Value in binary coded form for cfg_vin2a_fld0_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OUT                    (0xB78U)

/* Delay Select Value in binary coded form for cfg_vin2a_hsync0_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_IN                   (0xB7CU)

/* Delay Select Value in binary coded form for cfg_vin2a_hsync0_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OEN                  (0xB80U)

/* Delay Select Value in binary coded form for cfg_vin2a_hsync0_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OUT                  (0xB84U)

/* Delay Select Value in binary coded form for cfg_vin2a_vsync0_in interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_IN                   (0xB88U)

/* Delay Select Value in binary coded form for cfg_vin2a_vsync0_oen interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OEN                  (0xB8CU)

/* Delay Select Value in binary coded form for cfg_vin2a_vsync0_out interface */
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OUT                  (0xB90U)

/* Delay Select Value in binary coded form for cfg_vout1_clk_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_IN                      (0xB94U)

/* Delay Select Value in binary coded form for cfg_vout1_clk_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OEN                     (0xB98U)

/* Delay Select Value in binary coded form for cfg_vout1_clk_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OUT                     (0xB9CU)

/* Delay Select Value in binary coded form for cfg_vout1_d0_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_IN                       (0xBA0U)

/* Delay Select Value in binary coded form for cfg_vout1_d0_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OEN                      (0xBA4U)

/* Delay Select Value in binary coded form for cfg_vout1_d0_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OUT                      (0xBA8U)

/* Delay Select Value in binary coded form for cfg_vout1_d10_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_IN                      (0xBACU)

/* Delay Select Value in binary coded form for cfg_vout1_d10_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OEN                     (0xBB0U)

/* Delay Select Value in binary coded form for cfg_vout1_d10_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OUT                     (0xBB4U)

/* Delay Select Value in binary coded form for cfg_vout1_d11_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_IN                      (0xBB8U)

/* Delay Select Value in binary coded form for cfg_vout1_d11_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OEN                     (0xBBCU)

/* Delay Select Value in binary coded form for cfg_vout1_d11_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OUT                     (0xBC0U)

/* Delay Select Value in binary coded form for cfg_vout1_d12_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_IN                      (0xBC4U)

/* Delay Select Value in binary coded form for cfg_vout1_d12_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OEN                     (0xBC8U)

/* Delay Select Value in binary coded form for cfg_vout1_d12_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OUT                     (0xBCCU)

/* Delay Select Value in binary coded form for cfg_vout1_d13_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_IN                      (0xBD0U)

/* Delay Select Value in binary coded form for cfg_vout1_d13_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OEN                     (0xBD4U)

/* Delay Select Value in binary coded form for cfg_vout1_d13_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OUT                     (0xBD8U)

/* Delay Select Value in binary coded form for cfg_vout1_d14_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_IN                      (0xBDCU)

/* Delay Select Value in binary coded form for cfg_vout1_d14_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OEN                     (0xBE0U)

/* Delay Select Value in binary coded form for cfg_vout1_d14_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OUT                     (0xBE4U)

/* Delay Select Value in binary coded form for cfg_vout1_d15_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_IN                      (0xBE8U)

/* Delay Select Value in binary coded form for cfg_vout1_d15_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OEN                     (0xBECU)

/* Delay Select Value in binary coded form for cfg_vout1_d15_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OUT                     (0xBF0U)

/* Delay Select Value in binary coded form for cfg_vout1_d16_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_IN                      (0xBF4U)

/* Delay Select Value in binary coded form for cfg_vout1_d16_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OEN                     (0xBF8U)

/* Delay Select Value in binary coded form for cfg_vout1_d16_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OUT                     (0xBFCU)

/* Delay Select Value in binary coded form for cfg_vout1_d17_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_IN                      (0xC00U)

/* Delay Select Value in binary coded form for cfg_vout1_d17_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OEN                     (0xC04U)

/* Delay Select Value in binary coded form for cfg_vout1_d17_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OUT                     (0xC08U)

/* Delay Select Value in binary coded form for cfg_vout1_d18_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_IN                      (0xC0CU)

/* Delay Select Value in binary coded form for cfg_vout1_d18_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OEN                     (0xC10U)

/* Delay Select Value in binary coded form for cfg_vout1_d18_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OUT                     (0xC14U)

/* Delay Select Value in binary coded form for cfg_vout1_d19_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_IN                      (0xC18U)

/* Delay Select Value in binary coded form for cfg_vout1_d19_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OEN                     (0xC1CU)

/* Delay Select Value in binary coded form for cfg_vout1_d19_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OUT                     (0xC20U)

/* Delay Select Value in binary coded form for cfg_vout1_d1_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_IN                       (0xC24U)

/* Delay Select Value in binary coded form for cfg_vout1_d1_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OEN                      (0xC28U)

/* Delay Select Value in binary coded form for cfg_vout1_d1_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OUT                      (0xC2CU)

/* Delay Select Value in binary coded form for cfg_vout1_d20_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_IN                      (0xC30U)

/* Delay Select Value in binary coded form for cfg_vout1_d20_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OEN                     (0xC34U)

/* Delay Select Value in binary coded form for cfg_vout1_d20_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OUT                     (0xC38U)

/* Delay Select Value in binary coded form for cfg_vout1_d21_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_IN                      (0xC3CU)

/* Delay Select Value in binary coded form for cfg_vout1_d21_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OEN                     (0xC40U)

/* Delay Select Value in binary coded form for cfg_vout1_d21_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OUT                     (0xC44U)

/* Delay Select Value in binary coded form for cfg_vout1_d22_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_IN                      (0xC48U)

/* Delay Select Value in binary coded form for cfg_vout1_d22_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OEN                     (0xC4CU)

/* Delay Select Value in binary coded form for cfg_vout1_d22_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OUT                     (0xC50U)

/* Delay Select Value in binary coded form for cfg_vout1_d23_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_IN                      (0xC54U)

/* Delay Select Value in binary coded form for cfg_vout1_d23_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OEN                     (0xC58U)

/* Delay Select Value in binary coded form for cfg_vout1_d23_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OUT                     (0xC5CU)

/* Delay Select Value in binary coded form for cfg_vout1_d2_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_IN                       (0xC60U)

/* Delay Select Value in binary coded form for cfg_vout1_d2_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OEN                      (0xC64U)

/* Delay Select Value in binary coded form for cfg_vout1_d2_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OUT                      (0xC68U)

/* Delay Select Value in binary coded form for cfg_vout1_d3_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_IN                       (0xC6CU)

/* Delay Select Value in binary coded form for cfg_vout1_d3_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OEN                      (0xC70U)

/* Delay Select Value in binary coded form for cfg_vout1_d3_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OUT                      (0xC74U)

/* Delay Select Value in binary coded form for cfg_vout1_d4_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_IN                       (0xC78U)

/* Delay Select Value in binary coded form for cfg_vout1_d4_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OEN                      (0xC7CU)

/* Delay Select Value in binary coded form for cfg_vout1_d4_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OUT                      (0xC80U)

/* Delay Select Value in binary coded form for cfg_vout1_d5_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_IN                       (0xC84U)

/* Delay Select Value in binary coded form for cfg_vout1_d5_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OEN                      (0xC88U)

/* Delay Select Value in binary coded form for cfg_vout1_d5_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OUT                      (0xC8CU)

/* Delay Select Value in binary coded form for cfg_vout1_d6_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_IN                       (0xC90U)

/* Delay Select Value in binary coded form for cfg_vout1_d6_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OEN                      (0xC94U)

/* Delay Select Value in binary coded form for cfg_vout1_d6_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OUT                      (0xC98U)

/* Delay Select Value in binary coded form for cfg_vout1_d7_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_IN                       (0xC9CU)

/* Delay Select Value in binary coded form for cfg_vout1_d7_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OEN                      (0xCA0U)

/* Delay Select Value in binary coded form for cfg_vout1_d7_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OUT                      (0xCA4U)

/* Delay Select Value in binary coded form for cfg_vout1_d8_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_IN                       (0xCA8U)

/* Delay Select Value in binary coded form for cfg_vout1_d8_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OEN                      (0xCACU)

/* Delay Select Value in binary coded form for cfg_vout1_d8_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OUT                      (0xCB0U)

/* Delay Select Value in binary coded form for cfg_vout1_d9_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_IN                       (0xCB4U)

/* Delay Select Value in binary coded form for cfg_vout1_d9_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OEN                      (0xCB8U)

/* Delay Select Value in binary coded form for cfg_vout1_d9_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OUT                      (0xCBCU)

/* Delay Select Value in binary coded form for cfg_vout1_de_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_IN                       (0xCC0U)

/* Delay Select Value in binary coded form for cfg_vout1_de_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OEN                      (0xCC4U)

/* Delay Select Value in binary coded form for cfg_vout1_de_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OUT                      (0xCC8U)

/* Delay Select Value in binary coded form for cfg_vout1_fld_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_IN                      (0xCCCU)

/* Delay Select Value in binary coded form for cfg_vout1_fld_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OEN                     (0xCD0U)

/* Delay Select Value in binary coded form for cfg_vout1_fld_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OUT                     (0xCD4U)

/* Delay Select Value in binary coded form for cfg_vout1_hsync_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_IN                    (0xCD8U)

/* Delay Select Value in binary coded form for cfg_vout1_hsync_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OEN                   (0xCDCU)

/* Delay Select Value in binary coded form for cfg_vout1_hsync_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OUT                   (0xCE0U)

/* Delay Select Value in binary coded form for cfg_vout1_vsync_in interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_IN                    (0xCE4U)

/* Delay Select Value in binary coded form for cfg_vout1_vsync_oen interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OEN                   (0xCE8U)

/* Delay Select Value in binary coded form for cfg_vout1_vsync_out interface */
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OUT                   (0xCECU)

/* Delay Select Value in binary coded form for cfg_xref_clk0_in interface */
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_IN                      (0xCF0U)

/* Delay Select Value in binary coded form for cfg_xref_clk0_oen interface */
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OEN                     (0xCF4U)

/* Delay Select Value in binary coded form for cfg_xref_clk0_out interface */
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OUT                     (0xCF8U)

/* Delay Select Value in binary coded form for cfg_xref_clk1_in interface */
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_IN                      (0xCFCU)

/* Delay Select Value in binary coded form for cfg_xref_clk1_oen interface */
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OEN                     (0xD00U)

/* Delay Select Value in binary coded form for cfg_xref_clk1_out interface */
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OUT                     (0xD04U)

/* Delay Select Value in binary coded form for cfg_xref_clk2_in interface */
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_IN                      (0xD08U)

/* Delay Select Value in binary coded form for cfg_xref_clk2_oen interface */
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OEN                     (0xD0CU)

/* Delay Select Value in binary coded form for cfg_xref_clk2_out interface */
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OUT                     (0xD10U)

/* Delay Select Value in binary coded form for cfg_xref_clk3_in interface */
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_IN                      (0xD14U)

/* Delay Select Value in binary coded form for cfg_xref_clk3_oen interface */
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OEN                     (0xD18U)

/* Delay Select Value in binary coded form for cfg_xref_clk3_out interface */
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OUT                     (0xD1CU)


/**************************************************************************
* Field Definition Macros
**************************************************************************/

/* IP_REVISION */

#define CSL_IODELAYCONFIG_IP_REVISION_IP_REVISION_MASK          (0xFFFFFFFFU)
#define CSL_IODELAYCONFIG_IP_REVISION_IP_REVISION_SHIFT         (0U)
#define CSL_IODELAYCONFIG_IP_REVISION_IP_REVISION_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_IP_REVISION_IP_REVISION_MAX           (0xffffffffU)

#define CSL_IODELAYCONFIG_IP_REVISION_RESETVAL                  (0x00000000U)

/* IP_HWINFO */

#define CSL_IODELAYCONFIG_IP_HWINFO_IP_HWINFO_MASK              (0xFFFFFFFFU)
#define CSL_IODELAYCONFIG_IP_HWINFO_IP_HWINFO_SHIFT             (0U)
#define CSL_IODELAYCONFIG_IP_HWINFO_IP_HWINFO_RESETVAL          (0x00000000U)
#define CSL_IODELAYCONFIG_IP_HWINFO_IP_HWINFO_MAX               (0xffffffffU)

#define CSL_IODELAYCONFIG_IP_HWINFO_RESETVAL                    (0x00000000U)

/* IP_SYSCONFIG */

#define CSL_IODELAYCONFIG_IP_SYSCONFIG_IP_SYSCONFIG_MASK        (0xFFFFFFFFU)
#define CSL_IODELAYCONFIG_IP_SYSCONFIG_IP_SYSCONFIG_SHIFT       (0U)
#define CSL_IODELAYCONFIG_IP_SYSCONFIG_IP_SYSCONFIG_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_IP_SYSCONFIG_IP_SYSCONFIG_MAX         (0xffffffffU)

#define CSL_IODELAYCONFIG_IP_SYSCONFIG_RESETVAL                 (0x00000000U)

/* CONFIG_REG_0 */

#define CSL_IODELAYCONFIG_CONFIG_REG_0_CALIBRATION_START_MASK   (0x00000001U)
#define CSL_IODELAYCONFIG_CONFIG_REG_0_CALIBRATION_START_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CONFIG_REG_0_CALIBRATION_START_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CONFIG_REG_0_CALIBRATION_START_MAX    (0x00000001U)

#define CSL_IODELAYCONFIG_CONFIG_REG_0_RESETVAL                 (0x00000000U)

/* CONFIG_REG_1 */

#define CSL_IODELAYCONFIG_CONFIG_REG_1_EXPECTED_COARSE_DELAY_MASK  (0xFFFF0000U)
#define CSL_IODELAYCONFIG_CONFIG_REG_1_EXPECTED_COARSE_DELAY_SHIFT  (16U)
#define CSL_IODELAYCONFIG_CONFIG_REG_1_EXPECTED_COARSE_DELAY_RESETVAL  (0x00000078U)
#define CSL_IODELAYCONFIG_CONFIG_REG_1_EXPECTED_COARSE_DELAY_MAX  (0x0000ffffU)

#define CSL_IODELAYCONFIG_CONFIG_REG_1_EXPECTED_FINE_DELAY_MASK  (0x0000FFFFU)
#define CSL_IODELAYCONFIG_CONFIG_REG_1_EXPECTED_FINE_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CONFIG_REG_1_EXPECTED_FINE_DELAY_RESETVAL  (0x00000006U)
#define CSL_IODELAYCONFIG_CONFIG_REG_1_EXPECTED_FINE_DELAY_MAX  (0x0000ffffU)

#define CSL_IODELAYCONFIG_CONFIG_REG_1_RESETVAL                 (0x00780006U)

/* CONFIG_REG_2 */

#define CSL_IODELAYCONFIG_CONFIG_REG_2_REFCLK_PERIOD_MASK       (0x0000FFFFU)
#define CSL_IODELAYCONFIG_CONFIG_REG_2_REFCLK_PERIOD_SHIFT      (0U)
#define CSL_IODELAYCONFIG_CONFIG_REG_2_REFCLK_PERIOD_RESETVAL   (0x000000faU)
#define CSL_IODELAYCONFIG_CONFIG_REG_2_REFCLK_PERIOD_MAX        (0x0000ffffU)

#define CSL_IODELAYCONFIG_CONFIG_REG_2_RESETVAL                 (0x000000faU)

/* CONFIG_REG_3 */

#define CSL_IODELAYCONFIG_CONFIG_REG_3_COARSE_DELAY_COUNT_MASK  (0xFFFF0000U)
#define CSL_IODELAYCONFIG_CONFIG_REG_3_COARSE_DELAY_COUNT_SHIFT  (16U)
#define CSL_IODELAYCONFIG_CONFIG_REG_3_COARSE_DELAY_COUNT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CONFIG_REG_3_COARSE_DELAY_COUNT_MAX   (0x0000ffffU)

#define CSL_IODELAYCONFIG_CONFIG_REG_3_COARSE_REF_COUNT_MASK    (0x0000FFFFU)
#define CSL_IODELAYCONFIG_CONFIG_REG_3_COARSE_REF_COUNT_SHIFT   (0U)
#define CSL_IODELAYCONFIG_CONFIG_REG_3_COARSE_REF_COUNT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CONFIG_REG_3_COARSE_REF_COUNT_MAX     (0x0000ffffU)

#define CSL_IODELAYCONFIG_CONFIG_REG_3_RESETVAL                 (0x00000000U)

/* CONFIG_REG_4 */

#define CSL_IODELAYCONFIG_CONFIG_REG_4_FINE_REF_COUNT_MASK      (0x0000FFFFU)
#define CSL_IODELAYCONFIG_CONFIG_REG_4_FINE_REF_COUNT_SHIFT     (0U)
#define CSL_IODELAYCONFIG_CONFIG_REG_4_FINE_REF_COUNT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CONFIG_REG_4_FINE_REF_COUNT_MAX       (0x0000ffffU)

#define CSL_IODELAYCONFIG_CONFIG_REG_4_FINE_DELAY_COUNT_MASK    (0xFFFF0000U)
#define CSL_IODELAYCONFIG_CONFIG_REG_4_FINE_DELAY_COUNT_SHIFT   (16U)
#define CSL_IODELAYCONFIG_CONFIG_REG_4_FINE_DELAY_COUNT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CONFIG_REG_4_FINE_DELAY_COUNT_MAX     (0x0000ffffU)

#define CSL_IODELAYCONFIG_CONFIG_REG_4_RESETVAL                 (0x00000000U)

/* CONFIG_REG_5 */

#define CSL_IODELAYCONFIG_CONFIG_REG_5_COARSE_DELAY_SELECT_MASK  (0x0000001FU)
#define CSL_IODELAYCONFIG_CONFIG_REG_5_COARSE_DELAY_SELECT_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CONFIG_REG_5_COARSE_DELAY_SELECT_RESETVAL  (0x0000001fU)
#define CSL_IODELAYCONFIG_CONFIG_REG_5_COARSE_DELAY_SELECT_MAX  (0x0000001fU)

#define CSL_IODELAYCONFIG_CONFIG_REG_5_FINE_DELAY_SELECT_MASK   (0x00FF0000U)
#define CSL_IODELAYCONFIG_CONFIG_REG_5_FINE_DELAY_SELECT_SHIFT  (16U)
#define CSL_IODELAYCONFIG_CONFIG_REG_5_FINE_DELAY_SELECT_RESETVAL  (0x000000ffU)
#define CSL_IODELAYCONFIG_CONFIG_REG_5_FINE_DELAY_SELECT_MAX    (0x000000ffU)

#define CSL_IODELAYCONFIG_CONFIG_REG_5_RESETVAL                 (0x00ff001fU)

/* CONFIG_REG_6 */

#define CSL_IODELAYCONFIG_CONFIG_REG_6_COARSE_CALIB_WAIT_COUNT_MASK  (0x0000FFFFU)
#define CSL_IODELAYCONFIG_CONFIG_REG_6_COARSE_CALIB_WAIT_COUNT_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CONFIG_REG_6_COARSE_CALIB_WAIT_COUNT_RESETVAL  (0x0000ffffU)
#define CSL_IODELAYCONFIG_CONFIG_REG_6_COARSE_CALIB_WAIT_COUNT_MAX  (0x0000ffffU)

#define CSL_IODELAYCONFIG_CONFIG_REG_6_FINE_CALIB_WAIT_COUNT_MASK  (0xFFFF0000U)
#define CSL_IODELAYCONFIG_CONFIG_REG_6_FINE_CALIB_WAIT_COUNT_SHIFT  (16U)
#define CSL_IODELAYCONFIG_CONFIG_REG_6_FINE_CALIB_WAIT_COUNT_RESETVAL  (0x0000ffffU)
#define CSL_IODELAYCONFIG_CONFIG_REG_6_FINE_CALIB_WAIT_COUNT_MAX  (0x0000ffffU)

#define CSL_IODELAYCONFIG_CONFIG_REG_6_RESETVAL                 (0xffffffffU)

/* CONFIG_REG_7 */

#define CSL_IODELAYCONFIG_CONFIG_REG_7_COARSE_CALIB_PROC_COUNT_MASK  (0x0000FFFFU)
#define CSL_IODELAYCONFIG_CONFIG_REG_7_COARSE_CALIB_PROC_COUNT_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CONFIG_REG_7_COARSE_CALIB_PROC_COUNT_RESETVAL  (0x0000ffffU)
#define CSL_IODELAYCONFIG_CONFIG_REG_7_COARSE_CALIB_PROC_COUNT_MAX  (0x0000ffffU)

#define CSL_IODELAYCONFIG_CONFIG_REG_7_FINE_CALIB_PROC_COUNT_MASK  (0xFFFF0000U)
#define CSL_IODELAYCONFIG_CONFIG_REG_7_FINE_CALIB_PROC_COUNT_SHIFT  (16U)
#define CSL_IODELAYCONFIG_CONFIG_REG_7_FINE_CALIB_PROC_COUNT_RESETVAL  (0x0000ffffU)
#define CSL_IODELAYCONFIG_CONFIG_REG_7_FINE_CALIB_PROC_COUNT_MAX  (0x0000ffffU)

#define CSL_IODELAYCONFIG_CONFIG_REG_7_RESETVAL                 (0xffffffffU)

/* CONFIG_REG_8 */

#define CSL_IODELAYCONFIG_CONFIG_REG_8_GLOBAL_LOCK_BIT_MASK     (0x00000001U)
#define CSL_IODELAYCONFIG_CONFIG_REG_8_GLOBAL_LOCK_BIT_SHIFT    (0U)
#define CSL_IODELAYCONFIG_CONFIG_REG_8_GLOBAL_LOCK_BIT_RESETVAL  (0x00000001U)
#define CSL_IODELAYCONFIG_CONFIG_REG_8_GLOBAL_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CONFIG_REG_8_RESETVAL                 (0x00000001U)

/* CFG_RMII_MHZ_50_CLK_IN */

#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_IN_LOCK_BIT_MASK  (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_IN_LOCK_BIT_SHIFT  (10U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_IN_LOCK_BIT_MAX   (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_IN_SIGNATURE_MASK  (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_IN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_IN_SIGNATURE_MAX  (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_IN_RESETVAL       (0x00000000U)

/* CFG_RMII_MHZ_50_CLK_OEN */

#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OEN_LOCK_BIT_MASK  (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OEN_LOCK_BIT_SHIFT  (10U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OEN_LOCK_BIT_MAX  (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OEN_SIGNATURE_MASK  (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OEN_SIGNATURE_MAX  (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OEN_RESETVAL      (0x00000000U)

/* CFG_RMII_MHZ_50_CLK_OUT */

#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OUT_LOCK_BIT_MASK  (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OUT_LOCK_BIT_SHIFT  (10U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OUT_LOCK_BIT_MAX  (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OUT_SIGNATURE_MASK  (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OUT_SIGNATURE_MAX  (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RMII_MHZ_50_CLK_OUT_RESETVAL      (0x00000000U)

/* CFG_WAKEUP0_IN */

#define CSL_IODELAYCONFIG_CFG_WAKEUP0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP0_IN_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_IN_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_IN_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_IN_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_WAKEUP0_IN_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_IN_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_IN_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_IN_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP0_IN_RESETVAL               (0x00000000U)

/* CFG_WAKEUP0_OEN */

#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OEN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OEN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OEN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OEN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OEN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OEN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OEN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OEN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OEN_RESETVAL              (0x00000000U)

/* CFG_WAKEUP0_OUT */

#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OUT_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OUT_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OUT_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OUT_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OUT_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OUT_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OUT_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OUT_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP0_OUT_RESETVAL              (0x00000000U)

/* CFG_WAKEUP1_IN */

#define CSL_IODELAYCONFIG_CFG_WAKEUP1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP1_IN_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_IN_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_IN_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_IN_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_WAKEUP1_IN_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_IN_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_IN_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_IN_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP1_IN_RESETVAL               (0x00000000U)

/* CFG_WAKEUP1_OEN */

#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OEN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OEN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OEN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OEN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OEN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OEN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OEN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OEN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OEN_RESETVAL              (0x00000000U)

/* CFG_WAKEUP1_OUT */

#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OUT_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OUT_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OUT_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OUT_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OUT_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OUT_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OUT_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OUT_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP1_OUT_RESETVAL              (0x00000000U)

/* CFG_WAKEUP2_IN */

#define CSL_IODELAYCONFIG_CFG_WAKEUP2_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP2_IN_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_IN_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_IN_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_IN_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_WAKEUP2_IN_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_IN_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_IN_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_IN_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP2_IN_RESETVAL               (0x00000000U)

/* CFG_WAKEUP2_OEN */

#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OEN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OEN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OEN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OEN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OEN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OEN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OEN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OEN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OEN_RESETVAL              (0x00000000U)

/* CFG_WAKEUP2_OUT */

#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OUT_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OUT_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OUT_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OUT_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OUT_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OUT_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OUT_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OUT_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP2_OUT_RESETVAL              (0x00000000U)

/* CFG_WAKEUP3_IN */

#define CSL_IODELAYCONFIG_CFG_WAKEUP3_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP3_IN_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_IN_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_IN_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_IN_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_WAKEUP3_IN_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_IN_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_IN_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_IN_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP3_IN_RESETVAL               (0x00000000U)

/* CFG_WAKEUP3_OEN */

#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OEN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OEN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OEN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OEN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OEN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OEN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OEN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OEN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OEN_RESETVAL              (0x00000000U)

/* CFG_WAKEUP3_OUT */

#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OUT_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OUT_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OUT_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OUT_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OUT_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OUT_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OUT_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OUT_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_WAKEUP3_OUT_RESETVAL              (0x00000000U)

/* CFG_DCAN1_RX_IN */

#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_IN_RESETVAL              (0x00000000U)

/* CFG_DCAN1_RX_OEN */

#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OEN_RESETVAL             (0x00000000U)

/* CFG_DCAN1_RX_OUT */

#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_DCAN1_RX_OUT_RESETVAL             (0x00000000U)

/* CFG_DCAN1_TX_IN */

#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_IN_RESETVAL              (0x00000000U)

/* CFG_DCAN1_TX_OEN */

#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OEN_RESETVAL             (0x00000000U)

/* CFG_DCAN1_TX_OUT */

#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_DCAN1_TX_OUT_RESETVAL             (0x00000000U)

/* CFG_DCAN2_RX_IN */

#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_IN_RESETVAL              (0x00000000U)

/* CFG_DCAN2_RX_OEN */

#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OEN_RESETVAL             (0x00000000U)

/* CFG_DCAN2_RX_OUT */

#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_DCAN2_RX_OUT_RESETVAL             (0x00000000U)

/* CFG_DCAN2_TX_IN */

#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_IN_RESETVAL              (0x00000000U)

/* CFG_DCAN2_TX_OEN */

#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OEN_RESETVAL             (0x00000000U)

/* CFG_DCAN2_TX_OUT */

#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_DCAN2_TX_OUT_RESETVAL             (0x00000000U)

/* CFG_EMU0_IN */

#define CSL_IODELAYCONFIG_CFG_EMU0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_EMU0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_EMU0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU0_IN_COARSE_BINARY_DELAY_MAX   (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_EMU0_IN_LOCK_BIT_MASK             (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_EMU0_IN_LOCK_BIT_SHIFT            (10U)
#define CSL_IODELAYCONFIG_CFG_EMU0_IN_LOCK_BIT_RESETVAL         (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU0_IN_LOCK_BIT_MAX              (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_EMU0_IN_SIGNATURE_MASK            (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_EMU0_IN_SIGNATURE_SHIFT           (11U)
#define CSL_IODELAYCONFIG_CFG_EMU0_IN_SIGNATURE_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU0_IN_SIGNATURE_MAX             (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_EMU0_IN_RESETVAL                  (0x00000000U)

/* CFG_EMU0_OEN */

#define CSL_IODELAYCONFIG_CFG_EMU0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_EMU0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_EMU0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_EMU0_OEN_LOCK_BIT_MASK            (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_EMU0_OEN_LOCK_BIT_SHIFT           (10U)
#define CSL_IODELAYCONFIG_CFG_EMU0_OEN_LOCK_BIT_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU0_OEN_LOCK_BIT_MAX             (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_EMU0_OEN_SIGNATURE_MASK           (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_EMU0_OEN_SIGNATURE_SHIFT          (11U)
#define CSL_IODELAYCONFIG_CFG_EMU0_OEN_SIGNATURE_RESETVAL       (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU0_OEN_SIGNATURE_MAX            (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_EMU0_OEN_RESETVAL                 (0x00000000U)

/* CFG_EMU0_OUT */

#define CSL_IODELAYCONFIG_CFG_EMU0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_EMU0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_EMU0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_EMU0_OUT_LOCK_BIT_MASK            (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_EMU0_OUT_LOCK_BIT_SHIFT           (10U)
#define CSL_IODELAYCONFIG_CFG_EMU0_OUT_LOCK_BIT_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU0_OUT_LOCK_BIT_MAX             (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_EMU0_OUT_SIGNATURE_MASK           (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_EMU0_OUT_SIGNATURE_SHIFT          (11U)
#define CSL_IODELAYCONFIG_CFG_EMU0_OUT_SIGNATURE_RESETVAL       (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU0_OUT_SIGNATURE_MAX            (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_EMU0_OUT_RESETVAL                 (0x00000000U)

/* CFG_EMU1_IN */

#define CSL_IODELAYCONFIG_CFG_EMU1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_EMU1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_EMU1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU1_IN_COARSE_BINARY_DELAY_MAX   (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_EMU1_IN_LOCK_BIT_MASK             (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_EMU1_IN_LOCK_BIT_SHIFT            (10U)
#define CSL_IODELAYCONFIG_CFG_EMU1_IN_LOCK_BIT_RESETVAL         (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU1_IN_LOCK_BIT_MAX              (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_EMU1_IN_SIGNATURE_MASK            (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_EMU1_IN_SIGNATURE_SHIFT           (11U)
#define CSL_IODELAYCONFIG_CFG_EMU1_IN_SIGNATURE_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU1_IN_SIGNATURE_MAX             (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_EMU1_IN_RESETVAL                  (0x00000000U)

/* CFG_EMU1_OEN */

#define CSL_IODELAYCONFIG_CFG_EMU1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_EMU1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_EMU1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_EMU1_OEN_LOCK_BIT_MASK            (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_EMU1_OEN_LOCK_BIT_SHIFT           (10U)
#define CSL_IODELAYCONFIG_CFG_EMU1_OEN_LOCK_BIT_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU1_OEN_LOCK_BIT_MAX             (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_EMU1_OEN_SIGNATURE_MASK           (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_EMU1_OEN_SIGNATURE_SHIFT          (11U)
#define CSL_IODELAYCONFIG_CFG_EMU1_OEN_SIGNATURE_RESETVAL       (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU1_OEN_SIGNATURE_MAX            (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_EMU1_OEN_RESETVAL                 (0x00000000U)

/* CFG_EMU1_OUT */

#define CSL_IODELAYCONFIG_CFG_EMU1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_EMU1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_EMU1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_EMU1_OUT_LOCK_BIT_MASK            (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_EMU1_OUT_LOCK_BIT_SHIFT           (10U)
#define CSL_IODELAYCONFIG_CFG_EMU1_OUT_LOCK_BIT_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU1_OUT_LOCK_BIT_MAX             (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_EMU1_OUT_SIGNATURE_MASK           (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_EMU1_OUT_SIGNATURE_SHIFT          (11U)
#define CSL_IODELAYCONFIG_CFG_EMU1_OUT_SIGNATURE_RESETVAL       (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU1_OUT_SIGNATURE_MAX            (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_EMU1_OUT_RESETVAL                 (0x00000000U)

/* CFG_EMU2_IN */

#define CSL_IODELAYCONFIG_CFG_EMU2_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_EMU2_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_EMU2_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU2_IN_COARSE_BINARY_DELAY_MAX   (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_EMU2_IN_LOCK_BIT_MASK             (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_EMU2_IN_LOCK_BIT_SHIFT            (10U)
#define CSL_IODELAYCONFIG_CFG_EMU2_IN_LOCK_BIT_RESETVAL         (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU2_IN_LOCK_BIT_MAX              (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_EMU2_IN_SIGNATURE_MASK            (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_EMU2_IN_SIGNATURE_SHIFT           (11U)
#define CSL_IODELAYCONFIG_CFG_EMU2_IN_SIGNATURE_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU2_IN_SIGNATURE_MAX             (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_EMU2_IN_RESETVAL                  (0x00000000U)

/* CFG_EMU2_OEN */

#define CSL_IODELAYCONFIG_CFG_EMU2_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_EMU2_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_EMU2_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU2_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_EMU2_OEN_LOCK_BIT_MASK            (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_EMU2_OEN_LOCK_BIT_SHIFT           (10U)
#define CSL_IODELAYCONFIG_CFG_EMU2_OEN_LOCK_BIT_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU2_OEN_LOCK_BIT_MAX             (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_EMU2_OEN_SIGNATURE_MASK           (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_EMU2_OEN_SIGNATURE_SHIFT          (11U)
#define CSL_IODELAYCONFIG_CFG_EMU2_OEN_SIGNATURE_RESETVAL       (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU2_OEN_SIGNATURE_MAX            (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_EMU2_OEN_RESETVAL                 (0x00000000U)

/* CFG_EMU2_OUT */

#define CSL_IODELAYCONFIG_CFG_EMU2_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_EMU2_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_EMU2_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU2_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_EMU2_OUT_LOCK_BIT_MASK            (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_EMU2_OUT_LOCK_BIT_SHIFT           (10U)
#define CSL_IODELAYCONFIG_CFG_EMU2_OUT_LOCK_BIT_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU2_OUT_LOCK_BIT_MAX             (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_EMU2_OUT_SIGNATURE_MASK           (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_EMU2_OUT_SIGNATURE_SHIFT          (11U)
#define CSL_IODELAYCONFIG_CFG_EMU2_OUT_SIGNATURE_RESETVAL       (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU2_OUT_SIGNATURE_MAX            (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_EMU2_OUT_RESETVAL                 (0x00000000U)

/* CFG_EMU3_IN */

#define CSL_IODELAYCONFIG_CFG_EMU3_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_EMU3_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_EMU3_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU3_IN_COARSE_BINARY_DELAY_MAX   (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_EMU3_IN_LOCK_BIT_MASK             (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_EMU3_IN_LOCK_BIT_SHIFT            (10U)
#define CSL_IODELAYCONFIG_CFG_EMU3_IN_LOCK_BIT_RESETVAL         (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU3_IN_LOCK_BIT_MAX              (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_EMU3_IN_SIGNATURE_MASK            (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_EMU3_IN_SIGNATURE_SHIFT           (11U)
#define CSL_IODELAYCONFIG_CFG_EMU3_IN_SIGNATURE_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU3_IN_SIGNATURE_MAX             (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_EMU3_IN_RESETVAL                  (0x00000000U)

/* CFG_EMU3_OEN */

#define CSL_IODELAYCONFIG_CFG_EMU3_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_EMU3_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_EMU3_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU3_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_EMU3_OEN_LOCK_BIT_MASK            (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_EMU3_OEN_LOCK_BIT_SHIFT           (10U)
#define CSL_IODELAYCONFIG_CFG_EMU3_OEN_LOCK_BIT_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU3_OEN_LOCK_BIT_MAX             (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_EMU3_OEN_SIGNATURE_MASK           (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_EMU3_OEN_SIGNATURE_SHIFT          (11U)
#define CSL_IODELAYCONFIG_CFG_EMU3_OEN_SIGNATURE_RESETVAL       (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU3_OEN_SIGNATURE_MAX            (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_EMU3_OEN_RESETVAL                 (0x00000000U)

/* CFG_EMU3_OUT */

#define CSL_IODELAYCONFIG_CFG_EMU3_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_EMU3_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_EMU3_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU3_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_EMU3_OUT_LOCK_BIT_MASK            (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_EMU3_OUT_LOCK_BIT_SHIFT           (10U)
#define CSL_IODELAYCONFIG_CFG_EMU3_OUT_LOCK_BIT_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU3_OUT_LOCK_BIT_MAX             (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_EMU3_OUT_SIGNATURE_MASK           (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_EMU3_OUT_SIGNATURE_SHIFT          (11U)
#define CSL_IODELAYCONFIG_CFG_EMU3_OUT_SIGNATURE_RESETVAL       (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU3_OUT_SIGNATURE_MAX            (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_EMU3_OUT_RESETVAL                 (0x00000000U)

/* CFG_EMU4_IN */

#define CSL_IODELAYCONFIG_CFG_EMU4_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_EMU4_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_EMU4_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU4_IN_COARSE_BINARY_DELAY_MAX   (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_EMU4_IN_LOCK_BIT_MASK             (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_EMU4_IN_LOCK_BIT_SHIFT            (10U)
#define CSL_IODELAYCONFIG_CFG_EMU4_IN_LOCK_BIT_RESETVAL         (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU4_IN_LOCK_BIT_MAX              (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_EMU4_IN_SIGNATURE_MASK            (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_EMU4_IN_SIGNATURE_SHIFT           (11U)
#define CSL_IODELAYCONFIG_CFG_EMU4_IN_SIGNATURE_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU4_IN_SIGNATURE_MAX             (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_EMU4_IN_RESETVAL                  (0x00000000U)

/* CFG_EMU4_OEN */

#define CSL_IODELAYCONFIG_CFG_EMU4_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_EMU4_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_EMU4_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU4_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_EMU4_OEN_LOCK_BIT_MASK            (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_EMU4_OEN_LOCK_BIT_SHIFT           (10U)
#define CSL_IODELAYCONFIG_CFG_EMU4_OEN_LOCK_BIT_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU4_OEN_LOCK_BIT_MAX             (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_EMU4_OEN_SIGNATURE_MASK           (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_EMU4_OEN_SIGNATURE_SHIFT          (11U)
#define CSL_IODELAYCONFIG_CFG_EMU4_OEN_SIGNATURE_RESETVAL       (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU4_OEN_SIGNATURE_MAX            (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_EMU4_OEN_RESETVAL                 (0x00000000U)

/* CFG_EMU4_OUT */

#define CSL_IODELAYCONFIG_CFG_EMU4_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_EMU4_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_EMU4_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU4_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_EMU4_OUT_LOCK_BIT_MASK            (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_EMU4_OUT_LOCK_BIT_SHIFT           (10U)
#define CSL_IODELAYCONFIG_CFG_EMU4_OUT_LOCK_BIT_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU4_OUT_LOCK_BIT_MAX             (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_EMU4_OUT_SIGNATURE_MASK           (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_EMU4_OUT_SIGNATURE_SHIFT          (11U)
#define CSL_IODELAYCONFIG_CFG_EMU4_OUT_SIGNATURE_RESETVAL       (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_EMU4_OUT_SIGNATURE_MAX            (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_EMU4_OUT_RESETVAL                 (0x00000000U)

/* CFG_GPIO6_10_IN */

#define CSL_IODELAYCONFIG_CFG_GPIO6_10_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_10_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPIO6_10_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_10_IN_RESETVAL              (0x00000000U)

/* CFG_GPIO6_10_OEN */

#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OEN_RESETVAL             (0x00000000U)

/* CFG_GPIO6_10_OUT */

#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_10_OUT_RESETVAL             (0x00000000U)

/* CFG_GPIO6_11_IN */

#define CSL_IODELAYCONFIG_CFG_GPIO6_11_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_11_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPIO6_11_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_11_IN_RESETVAL              (0x00000000U)

/* CFG_GPIO6_11_OEN */

#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OEN_RESETVAL             (0x00000000U)

/* CFG_GPIO6_11_OUT */

#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_11_OUT_RESETVAL             (0x00000000U)

/* CFG_GPIO6_14_IN */

#define CSL_IODELAYCONFIG_CFG_GPIO6_14_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_14_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPIO6_14_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_14_IN_RESETVAL              (0x00000000U)

/* CFG_GPIO6_14_OEN */

#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OEN_RESETVAL             (0x00000000U)

/* CFG_GPIO6_14_OUT */

#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_14_OUT_RESETVAL             (0x00000000U)

/* CFG_GPIO6_15_IN */

#define CSL_IODELAYCONFIG_CFG_GPIO6_15_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_15_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPIO6_15_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_15_IN_RESETVAL              (0x00000000U)

/* CFG_GPIO6_15_OEN */

#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OEN_RESETVAL             (0x00000000U)

/* CFG_GPIO6_15_OUT */

#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_15_OUT_RESETVAL             (0x00000000U)

/* CFG_GPIO6_16_IN */

#define CSL_IODELAYCONFIG_CFG_GPIO6_16_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_16_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPIO6_16_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_16_IN_RESETVAL              (0x00000000U)

/* CFG_GPIO6_16_OEN */

#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OEN_RESETVAL             (0x00000000U)

/* CFG_GPIO6_16_OUT */

#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPIO6_16_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_A0_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A0_IN_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_IN_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_IN_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_IN_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A0_IN_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_IN_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_IN_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_IN_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A0_IN_RESETVAL               (0x00000000U)

/* CFG_GPMC_A0_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OEN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OEN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OEN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OEN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OEN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OEN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OEN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OEN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OEN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A0_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OUT_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OUT_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OUT_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OUT_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OUT_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OUT_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OUT_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OUT_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A0_OUT_RESETVAL              (0x00000000U)

/* CFG_GPMC_A10_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A10_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A10_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A10_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A10_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A10_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_A10_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A10_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_A11_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A11_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A11_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A11_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A11_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A11_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_A11_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A11_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_A12_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A12_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A12_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A12_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A12_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A12_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_A12_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A12_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_A13_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A13_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A13_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A13_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A13_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A13_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_A13_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A13_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_A14_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A14_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A14_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A14_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A14_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A14_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_A14_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A14_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_A15_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A15_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A15_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A15_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A15_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A15_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_A15_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A15_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_A16_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A16_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A16_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A16_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A16_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A16_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_A16_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A16_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_A17_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A17_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A17_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A17_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A17_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A17_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_A17_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A17_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_A18_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A18_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A18_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A18_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A18_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A18_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_A18_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A18_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_A19_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A19_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A19_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A19_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A19_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A19_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_A19_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A19_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_A1_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A1_IN_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_IN_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_IN_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_IN_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A1_IN_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_IN_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_IN_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_IN_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A1_IN_RESETVAL               (0x00000000U)

/* CFG_GPMC_A1_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OEN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OEN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OEN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OEN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OEN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OEN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OEN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OEN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OEN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A1_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OUT_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OUT_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OUT_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OUT_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OUT_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OUT_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OUT_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OUT_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A1_OUT_RESETVAL              (0x00000000U)

/* CFG_GPMC_A20_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A20_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A20_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A20_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A20_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A20_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_A20_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A20_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_A21_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A21_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A21_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A21_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A21_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A21_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_A21_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A21_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_A22_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A22_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A22_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A22_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A22_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A22_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_A22_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A22_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_A23_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A23_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A23_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A23_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A23_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A23_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_A23_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A23_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_A24_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A24_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A24_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A24_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A24_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A24_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_A24_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A24_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_A25_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A25_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A25_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A25_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A25_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A25_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_A25_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A25_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_A26_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A26_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A26_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A26_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A26_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A26_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_A26_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A26_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_A27_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A27_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A27_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A27_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A27_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A27_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_A27_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A27_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_A2_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A2_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A2_IN_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_IN_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_IN_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_IN_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A2_IN_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_IN_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_IN_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_IN_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A2_IN_RESETVAL               (0x00000000U)

/* CFG_GPMC_A2_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OEN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OEN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OEN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OEN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OEN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OEN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OEN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OEN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OEN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A2_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OUT_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OUT_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OUT_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OUT_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OUT_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OUT_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OUT_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OUT_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A2_OUT_RESETVAL              (0x00000000U)

/* CFG_GPMC_A3_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A3_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A3_IN_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_IN_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_IN_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_IN_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A3_IN_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_IN_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_IN_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_IN_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A3_IN_RESETVAL               (0x00000000U)

/* CFG_GPMC_A3_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OEN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OEN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OEN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OEN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OEN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OEN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OEN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OEN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OEN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A3_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OUT_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OUT_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OUT_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OUT_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OUT_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OUT_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OUT_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OUT_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A3_OUT_RESETVAL              (0x00000000U)

/* CFG_GPMC_A4_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A4_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A4_IN_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_IN_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_IN_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_IN_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A4_IN_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_IN_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_IN_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_IN_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A4_IN_RESETVAL               (0x00000000U)

/* CFG_GPMC_A4_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OEN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OEN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OEN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OEN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OEN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OEN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OEN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OEN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OEN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A4_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OUT_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OUT_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OUT_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OUT_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OUT_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OUT_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OUT_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OUT_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A4_OUT_RESETVAL              (0x00000000U)

/* CFG_GPMC_A5_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A5_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A5_IN_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_IN_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_IN_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_IN_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A5_IN_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_IN_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_IN_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_IN_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A5_IN_RESETVAL               (0x00000000U)

/* CFG_GPMC_A5_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OEN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OEN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OEN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OEN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OEN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OEN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OEN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OEN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OEN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A5_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OUT_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OUT_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OUT_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OUT_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OUT_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OUT_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OUT_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OUT_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A5_OUT_RESETVAL              (0x00000000U)

/* CFG_GPMC_A6_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A6_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A6_IN_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_IN_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_IN_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_IN_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A6_IN_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_IN_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_IN_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_IN_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A6_IN_RESETVAL               (0x00000000U)

/* CFG_GPMC_A6_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OEN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OEN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OEN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OEN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OEN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OEN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OEN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OEN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OEN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A6_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OUT_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OUT_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OUT_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OUT_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OUT_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OUT_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OUT_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OUT_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A6_OUT_RESETVAL              (0x00000000U)

/* CFG_GPMC_A7_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A7_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A7_IN_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_IN_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_IN_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_IN_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A7_IN_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_IN_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_IN_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_IN_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A7_IN_RESETVAL               (0x00000000U)

/* CFG_GPMC_A7_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OEN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OEN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OEN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OEN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OEN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OEN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OEN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OEN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OEN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A7_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OUT_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OUT_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OUT_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OUT_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OUT_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OUT_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OUT_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OUT_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A7_OUT_RESETVAL              (0x00000000U)

/* CFG_GPMC_A8_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A8_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A8_IN_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_IN_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_IN_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_IN_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A8_IN_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_IN_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_IN_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_IN_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A8_IN_RESETVAL               (0x00000000U)

/* CFG_GPMC_A8_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OEN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OEN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OEN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OEN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OEN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OEN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OEN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OEN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OEN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A8_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OUT_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OUT_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OUT_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OUT_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OUT_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OUT_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OUT_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OUT_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A8_OUT_RESETVAL              (0x00000000U)

/* CFG_GPMC_A9_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A9_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A9_IN_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_IN_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_IN_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_IN_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A9_IN_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_IN_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_IN_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_IN_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A9_IN_RESETVAL               (0x00000000U)

/* CFG_GPMC_A9_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OEN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OEN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OEN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OEN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OEN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OEN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OEN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OEN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OEN_RESETVAL              (0x00000000U)

/* CFG_GPMC_A9_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OUT_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OUT_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OUT_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OUT_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OUT_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OUT_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OUT_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OUT_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_A9_OUT_RESETVAL              (0x00000000U)

/* CFG_GPMC_AD0_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_AD0_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD0_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD0_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD10_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_IN_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD10_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OEN_RESETVAL            (0x00000000U)

/* CFG_GPMC_AD10_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD10_OUT_RESETVAL            (0x00000000U)

/* CFG_GPMC_AD11_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_IN_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD11_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OEN_RESETVAL            (0x00000000U)

/* CFG_GPMC_AD11_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD11_OUT_RESETVAL            (0x00000000U)

/* CFG_GPMC_AD12_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_IN_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD12_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OEN_RESETVAL            (0x00000000U)

/* CFG_GPMC_AD12_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD12_OUT_RESETVAL            (0x00000000U)

/* CFG_GPMC_AD13_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_IN_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD13_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OEN_RESETVAL            (0x00000000U)

/* CFG_GPMC_AD13_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD13_OUT_RESETVAL            (0x00000000U)

/* CFG_GPMC_AD14_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_IN_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD14_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OEN_RESETVAL            (0x00000000U)

/* CFG_GPMC_AD14_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD14_OUT_RESETVAL            (0x00000000U)

/* CFG_GPMC_AD15_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_IN_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD15_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OEN_RESETVAL            (0x00000000U)

/* CFG_GPMC_AD15_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD15_OUT_RESETVAL            (0x00000000U)

/* CFG_GPMC_AD1_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_AD1_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD1_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD1_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD2_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_AD2_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD2_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD2_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD3_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_AD3_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD3_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD3_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD4_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_AD4_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD4_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD4_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD5_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_AD5_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD5_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD5_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD6_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_AD6_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD6_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD6_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD7_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_AD7_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD7_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD7_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD8_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_AD8_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD8_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD8_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD9_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_AD9_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_AD9_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_AD9_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_ADVN_ALE_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_IN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_IN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_IN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_IN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_IN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_IN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_IN_RESETVAL         (0x00000000U)

/* CFG_GPMC_ADVN_ALE_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OEN_LOCK_BIT_MASK   (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OEN_LOCK_BIT_SHIFT  (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OEN_LOCK_BIT_MAX    (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OEN_SIGNATURE_MASK  (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OEN_SIGNATURE_MAX   (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OEN_RESETVAL        (0x00000000U)

/* CFG_GPMC_ADVN_ALE_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OUT_LOCK_BIT_MASK   (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OUT_LOCK_BIT_SHIFT  (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OUT_LOCK_BIT_MAX    (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OUT_SIGNATURE_MASK  (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OUT_SIGNATURE_MAX   (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_ADVN_ALE_OUT_RESETVAL        (0x00000000U)

/* CFG_GPMC_BEN0_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_IN_RESETVAL             (0x00000000U)

/* CFG_GPMC_BEN0_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OEN_RESETVAL            (0x00000000U)

/* CFG_GPMC_BEN0_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN0_OUT_RESETVAL            (0x00000000U)

/* CFG_GPMC_BEN1_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_IN_RESETVAL             (0x00000000U)

/* CFG_GPMC_BEN1_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OEN_RESETVAL            (0x00000000U)

/* CFG_GPMC_BEN1_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_BEN1_OUT_RESETVAL            (0x00000000U)

/* CFG_GPMC_CLK_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_CLK_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_CLK_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CLK_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_CS0_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_CS0_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_CS0_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS0_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_CS1_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_CS1_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_CS1_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS1_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_CS2_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_CS2_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_CS2_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS2_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_CS3_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_CS3_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_CS3_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_CS3_OUT_RESETVAL             (0x00000000U)

/* CFG_GPMC_OEN_REN_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_IN_RESETVAL          (0x00000000U)

/* CFG_GPMC_OEN_REN_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OEN_RESETVAL         (0x00000000U)

/* CFG_GPMC_OEN_REN_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_OEN_REN_OUT_RESETVAL         (0x00000000U)

/* CFG_GPMC_WAIT0_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_IN_RESETVAL            (0x00000000U)

/* CFG_GPMC_WAIT0_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OEN_RESETVAL           (0x00000000U)

/* CFG_GPMC_WAIT0_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_WAIT0_OUT_RESETVAL           (0x00000000U)

/* CFG_GPMC_WEN_IN */

#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_IN_RESETVAL              (0x00000000U)

/* CFG_GPMC_WEN_OEN */

#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OEN_RESETVAL             (0x00000000U)

/* CFG_GPMC_WEN_OUT */

#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_GPMC_WEN_OUT_RESETVAL             (0x00000000U)

/* CFG_MCASP1_ACLKR_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_IN_RESETVAL          (0x00000000U)

/* CFG_MCASP1_ACLKR_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OEN_RESETVAL         (0x00000000U)

/* CFG_MCASP1_ACLKR_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKR_OUT_RESETVAL         (0x00000000U)

/* CFG_MCASP1_ACLKX_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_IN_RESETVAL          (0x00000000U)

/* CFG_MCASP1_ACLKX_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OEN_RESETVAL         (0x00000000U)

/* CFG_MCASP1_ACLKX_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_ACLKX_OUT_RESETVAL         (0x00000000U)

/* CFG_MCASP1_AXR0_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP1_AXR0_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR0_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR0_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR10_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_IN_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR10_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OEN_RESETVAL         (0x00000000U)

/* CFG_MCASP1_AXR10_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR10_OUT_RESETVAL         (0x00000000U)

/* CFG_MCASP1_AXR11_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_IN_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR11_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OEN_RESETVAL         (0x00000000U)

/* CFG_MCASP1_AXR11_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR11_OUT_RESETVAL         (0x00000000U)

/* CFG_MCASP1_AXR12_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_IN_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR12_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OEN_RESETVAL         (0x00000000U)

/* CFG_MCASP1_AXR12_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR12_OUT_RESETVAL         (0x00000000U)

/* CFG_MCASP1_AXR13_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_IN_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR13_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OEN_RESETVAL         (0x00000000U)

/* CFG_MCASP1_AXR13_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR13_OUT_RESETVAL         (0x00000000U)

/* CFG_MCASP1_AXR14_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_IN_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR14_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OEN_RESETVAL         (0x00000000U)

/* CFG_MCASP1_AXR14_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR14_OUT_RESETVAL         (0x00000000U)

/* CFG_MCASP1_AXR15_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_IN_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR15_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OEN_RESETVAL         (0x00000000U)

/* CFG_MCASP1_AXR15_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR15_OUT_RESETVAL         (0x00000000U)

/* CFG_MCASP1_AXR1_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP1_AXR1_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR1_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR1_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR2_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP1_AXR2_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR2_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR2_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR3_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP1_AXR3_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR3_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR3_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR4_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP1_AXR4_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR4_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR4_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR5_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP1_AXR5_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR5_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR5_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR6_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP1_AXR6_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR6_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR6_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR7_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP1_AXR7_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR7_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR7_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR8_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP1_AXR8_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR8_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR8_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR9_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP1_AXR9_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP1_AXR9_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_AXR9_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP1_FSR_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_IN_RESETVAL            (0x00000000U)

/* CFG_MCASP1_FSR_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OEN_RESETVAL           (0x00000000U)

/* CFG_MCASP1_FSR_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSR_OUT_RESETVAL           (0x00000000U)

/* CFG_MCASP1_FSX_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_IN_RESETVAL            (0x00000000U)

/* CFG_MCASP1_FSX_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OEN_RESETVAL           (0x00000000U)

/* CFG_MCASP1_FSX_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP1_FSX_OUT_RESETVAL           (0x00000000U)

/* CFG_MCASP2_ACLKR_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_IN_RESETVAL          (0x00000000U)

/* CFG_MCASP2_ACLKR_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OEN_RESETVAL         (0x00000000U)

/* CFG_MCASP2_ACLKR_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKR_OUT_RESETVAL         (0x00000000U)

/* CFG_MCASP2_ACLKX_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_IN_RESETVAL          (0x00000000U)

/* CFG_MCASP2_ACLKX_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OEN_RESETVAL         (0x00000000U)

/* CFG_MCASP2_ACLKX_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_ACLKX_OUT_RESETVAL         (0x00000000U)

/* CFG_MCASP2_AXR0_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP2_AXR0_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP2_AXR0_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR0_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP2_AXR1_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP2_AXR1_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP2_AXR1_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR1_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP2_AXR2_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP2_AXR2_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP2_AXR2_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR2_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP2_AXR3_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP2_AXR3_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP2_AXR3_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR3_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP2_AXR4_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP2_AXR4_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP2_AXR4_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR4_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP2_AXR5_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP2_AXR5_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP2_AXR5_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR5_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP2_AXR6_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP2_AXR6_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP2_AXR6_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR6_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP2_AXR7_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP2_AXR7_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP2_AXR7_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_AXR7_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP2_FSR_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_IN_RESETVAL            (0x00000000U)

/* CFG_MCASP2_FSR_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OEN_RESETVAL           (0x00000000U)

/* CFG_MCASP2_FSR_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSR_OUT_RESETVAL           (0x00000000U)

/* CFG_MCASP2_FSX_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_IN_RESETVAL            (0x00000000U)

/* CFG_MCASP2_FSX_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OEN_RESETVAL           (0x00000000U)

/* CFG_MCASP2_FSX_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP2_FSX_OUT_RESETVAL           (0x00000000U)

/* CFG_MCASP3_ACLKX_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_IN_RESETVAL          (0x00000000U)

/* CFG_MCASP3_ACLKX_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OEN_RESETVAL         (0x00000000U)

/* CFG_MCASP3_ACLKX_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_ACLKX_OUT_RESETVAL         (0x00000000U)

/* CFG_MCASP3_AXR0_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP3_AXR0_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP3_AXR0_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR0_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP3_AXR1_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP3_AXR1_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP3_AXR1_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_AXR1_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP3_FSX_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_IN_RESETVAL            (0x00000000U)

/* CFG_MCASP3_FSX_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OEN_RESETVAL           (0x00000000U)

/* CFG_MCASP3_FSX_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP3_FSX_OUT_RESETVAL           (0x00000000U)

/* CFG_MCASP4_ACLKX_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_IN_RESETVAL          (0x00000000U)

/* CFG_MCASP4_ACLKX_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OEN_RESETVAL         (0x00000000U)

/* CFG_MCASP4_ACLKX_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_ACLKX_OUT_RESETVAL         (0x00000000U)

/* CFG_MCASP4_AXR0_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP4_AXR0_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP4_AXR0_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR0_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP4_AXR1_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP4_AXR1_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP4_AXR1_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_AXR1_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP4_FSX_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_IN_RESETVAL            (0x00000000U)

/* CFG_MCASP4_FSX_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OEN_RESETVAL           (0x00000000U)

/* CFG_MCASP4_FSX_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP4_FSX_OUT_RESETVAL           (0x00000000U)

/* CFG_MCASP5_ACLKX_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_IN_RESETVAL          (0x00000000U)

/* CFG_MCASP5_ACLKX_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OEN_RESETVAL         (0x00000000U)

/* CFG_MCASP5_ACLKX_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_ACLKX_OUT_RESETVAL         (0x00000000U)

/* CFG_MCASP5_AXR0_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP5_AXR0_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP5_AXR0_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR0_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP5_AXR1_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_IN_RESETVAL           (0x00000000U)

/* CFG_MCASP5_AXR1_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OEN_RESETVAL          (0x00000000U)

/* CFG_MCASP5_AXR1_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_AXR1_OUT_RESETVAL          (0x00000000U)

/* CFG_MCASP5_FSX_IN */

#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_IN_RESETVAL            (0x00000000U)

/* CFG_MCASP5_FSX_OEN */

#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OEN_RESETVAL           (0x00000000U)

/* CFG_MCASP5_FSX_OUT */

#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MCASP5_FSX_OUT_RESETVAL           (0x00000000U)

/* CFG_MDIO_D_IN */

#define CSL_IODELAYCONFIG_CFG_MDIO_D_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MDIO_D_IN_LOCK_BIT_MASK           (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_IN_LOCK_BIT_SHIFT          (10U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_IN_LOCK_BIT_RESETVAL       (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_IN_LOCK_BIT_MAX            (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MDIO_D_IN_SIGNATURE_MASK          (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_IN_SIGNATURE_SHIFT         (11U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_IN_SIGNATURE_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_IN_SIGNATURE_MAX           (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MDIO_D_IN_RESETVAL                (0x00000000U)

/* CFG_MDIO_D_OEN */

#define CSL_IODELAYCONFIG_CFG_MDIO_D_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MDIO_D_OEN_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OEN_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OEN_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OEN_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MDIO_D_OEN_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OEN_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OEN_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OEN_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MDIO_D_OEN_RESETVAL               (0x00000000U)

/* CFG_MDIO_D_OUT */

#define CSL_IODELAYCONFIG_CFG_MDIO_D_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MDIO_D_OUT_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OUT_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OUT_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OUT_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MDIO_D_OUT_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OUT_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OUT_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MDIO_D_OUT_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MDIO_D_OUT_RESETVAL               (0x00000000U)

/* CFG_MDIO_MCLK_IN */

#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_IN_RESETVAL             (0x00000000U)

/* CFG_MDIO_MCLK_OEN */

#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OEN_RESETVAL            (0x00000000U)

/* CFG_MDIO_MCLK_OUT */

#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MDIO_MCLK_OUT_RESETVAL            (0x00000000U)

/* CFG_MLBP_CLK_N_IN */

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_IN_RESETVAL            (0x00000000U)

/* CFG_MLBP_CLK_N_OEN */

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OEN_RESETVAL           (0x00000000U)

/* CFG_MLBP_CLK_N_OUT */

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_N_OUT_RESETVAL           (0x00000000U)

/* CFG_MLBP_CLK_P_IN */

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_IN_RESETVAL            (0x00000000U)

/* CFG_MLBP_CLK_P_OEN */

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OEN_RESETVAL           (0x00000000U)

/* CFG_MLBP_CLK_P_OUT */

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MLBP_CLK_P_OUT_RESETVAL           (0x00000000U)

/* CFG_MLBP_DAT_N_IN */

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_IN_RESETVAL            (0x00000000U)

/* CFG_MLBP_DAT_N_OEN */

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OEN_RESETVAL           (0x00000000U)

/* CFG_MLBP_DAT_N_OUT */

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_N_OUT_RESETVAL           (0x00000000U)

/* CFG_MLBP_DAT_P_IN */

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_IN_RESETVAL            (0x00000000U)

/* CFG_MLBP_DAT_P_OEN */

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OEN_RESETVAL           (0x00000000U)

/* CFG_MLBP_DAT_P_OUT */

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MLBP_DAT_P_OUT_RESETVAL           (0x00000000U)

/* CFG_MLBP_SIG_N_IN */

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_IN_RESETVAL            (0x00000000U)

/* CFG_MLBP_SIG_N_OEN */

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OEN_RESETVAL           (0x00000000U)

/* CFG_MLBP_SIG_N_OUT */

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_N_OUT_RESETVAL           (0x00000000U)

/* CFG_MLBP_SIG_P_IN */

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_IN_RESETVAL            (0x00000000U)

/* CFG_MLBP_SIG_P_OEN */

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OEN_RESETVAL           (0x00000000U)

/* CFG_MLBP_SIG_P_OUT */

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MLBP_SIG_P_OUT_RESETVAL           (0x00000000U)

/* CFG_MMC1_CLK_IN */

#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_IN_RESETVAL              (0x00000000U)

/* CFG_MMC1_CLK_OEN */

#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OEN_RESETVAL             (0x00000000U)

/* CFG_MMC1_CLK_OUT */

#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_CLK_OUT_RESETVAL             (0x00000000U)

/* CFG_MMC1_CMD_IN */

#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_IN_RESETVAL              (0x00000000U)

/* CFG_MMC1_CMD_OEN */

#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OEN_RESETVAL             (0x00000000U)

/* CFG_MMC1_CMD_OUT */

#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_CMD_OUT_RESETVAL             (0x00000000U)

/* CFG_MMC1_DAT0_IN */

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_IN_RESETVAL             (0x00000000U)

/* CFG_MMC1_DAT0_OEN */

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OEN_RESETVAL            (0x00000000U)

/* CFG_MMC1_DAT0_OUT */

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT0_OUT_RESETVAL            (0x00000000U)

/* CFG_MMC1_DAT1_IN */

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_IN_RESETVAL             (0x00000000U)

/* CFG_MMC1_DAT1_OEN */

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OEN_RESETVAL            (0x00000000U)

/* CFG_MMC1_DAT1_OUT */

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT1_OUT_RESETVAL            (0x00000000U)

/* CFG_MMC1_DAT2_IN */

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_IN_RESETVAL             (0x00000000U)

/* CFG_MMC1_DAT2_OEN */

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OEN_RESETVAL            (0x00000000U)

/* CFG_MMC1_DAT2_OUT */

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT2_OUT_RESETVAL            (0x00000000U)

/* CFG_MMC1_DAT3_IN */

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_IN_RESETVAL             (0x00000000U)

/* CFG_MMC1_DAT3_OEN */

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OEN_RESETVAL            (0x00000000U)

/* CFG_MMC1_DAT3_OUT */

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_DAT3_OUT_RESETVAL            (0x00000000U)

/* CFG_MMC1_SDCD_IN */

#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_IN_RESETVAL             (0x00000000U)

/* CFG_MMC1_SDCD_OEN */

#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OEN_RESETVAL            (0x00000000U)

/* CFG_MMC1_SDCD_OUT */

#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_SDCD_OUT_RESETVAL            (0x00000000U)

/* CFG_MMC1_SDWP_IN */

#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_IN_RESETVAL             (0x00000000U)

/* CFG_MMC1_SDWP_OEN */

#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OEN_RESETVAL            (0x00000000U)

/* CFG_MMC1_SDWP_OUT */

#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC1_SDWP_OUT_RESETVAL            (0x00000000U)

/* CFG_MMC3_CLK_IN */

#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_IN_RESETVAL              (0x00000000U)

/* CFG_MMC3_CLK_OEN */

#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OEN_RESETVAL             (0x00000000U)

/* CFG_MMC3_CLK_OUT */

#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_CLK_OUT_RESETVAL             (0x00000000U)

/* CFG_MMC3_CMD_IN */

#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_IN_RESETVAL              (0x00000000U)

/* CFG_MMC3_CMD_OEN */

#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OEN_RESETVAL             (0x00000000U)

/* CFG_MMC3_CMD_OUT */

#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_CMD_OUT_RESETVAL             (0x00000000U)

/* CFG_MMC3_DAT0_IN */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_IN_RESETVAL             (0x00000000U)

/* CFG_MMC3_DAT0_OEN */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OEN_RESETVAL            (0x00000000U)

/* CFG_MMC3_DAT0_OUT */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT0_OUT_RESETVAL            (0x00000000U)

/* CFG_MMC3_DAT1_IN */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_IN_RESETVAL             (0x00000000U)

/* CFG_MMC3_DAT1_OEN */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OEN_RESETVAL            (0x00000000U)

/* CFG_MMC3_DAT1_OUT */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT1_OUT_RESETVAL            (0x00000000U)

/* CFG_MMC3_DAT2_IN */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_IN_RESETVAL             (0x00000000U)

/* CFG_MMC3_DAT2_OEN */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OEN_RESETVAL            (0x00000000U)

/* CFG_MMC3_DAT2_OUT */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT2_OUT_RESETVAL            (0x00000000U)

/* CFG_MMC3_DAT3_IN */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_IN_RESETVAL             (0x00000000U)

/* CFG_MMC3_DAT3_OEN */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OEN_RESETVAL            (0x00000000U)

/* CFG_MMC3_DAT3_OUT */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT3_OUT_RESETVAL            (0x00000000U)

/* CFG_MMC3_DAT4_IN */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_IN_RESETVAL             (0x00000000U)

/* CFG_MMC3_DAT4_OEN */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OEN_RESETVAL            (0x00000000U)

/* CFG_MMC3_DAT4_OUT */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT4_OUT_RESETVAL            (0x00000000U)

/* CFG_MMC3_DAT5_IN */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_IN_RESETVAL             (0x00000000U)

/* CFG_MMC3_DAT5_OEN */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OEN_RESETVAL            (0x00000000U)

/* CFG_MMC3_DAT5_OUT */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT5_OUT_RESETVAL            (0x00000000U)

/* CFG_MMC3_DAT6_IN */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_IN_RESETVAL             (0x00000000U)

/* CFG_MMC3_DAT6_OEN */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OEN_RESETVAL            (0x00000000U)

/* CFG_MMC3_DAT6_OUT */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT6_OUT_RESETVAL            (0x00000000U)

/* CFG_MMC3_DAT7_IN */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_IN_RESETVAL             (0x00000000U)

/* CFG_MMC3_DAT7_OEN */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OEN_RESETVAL            (0x00000000U)

/* CFG_MMC3_DAT7_OUT */

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_MMC3_DAT7_OUT_RESETVAL            (0x00000000U)

/* CFG_RGMII0_RXC_IN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_IN_RESETVAL            (0x00000000U)

/* CFG_RGMII0_RXC_OEN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OEN_RESETVAL           (0x00000000U)

/* CFG_RGMII0_RXC_OUT */

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXC_OUT_RESETVAL           (0x00000000U)

/* CFG_RGMII0_RXCTL_IN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_IN_RESETVAL          (0x00000000U)

/* CFG_RGMII0_RXCTL_OEN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OEN_RESETVAL         (0x00000000U)

/* CFG_RGMII0_RXCTL_OUT */

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXCTL_OUT_RESETVAL         (0x00000000U)

/* CFG_RGMII0_RXD0_IN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_IN_RESETVAL           (0x00000000U)

/* CFG_RGMII0_RXD0_OEN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OEN_RESETVAL          (0x00000000U)

/* CFG_RGMII0_RXD0_OUT */

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD0_OUT_RESETVAL          (0x00000000U)

/* CFG_RGMII0_RXD1_IN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_IN_RESETVAL           (0x00000000U)

/* CFG_RGMII0_RXD1_OEN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OEN_RESETVAL          (0x00000000U)

/* CFG_RGMII0_RXD1_OUT */

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD1_OUT_RESETVAL          (0x00000000U)

/* CFG_RGMII0_RXD2_IN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_IN_RESETVAL           (0x00000000U)

/* CFG_RGMII0_RXD2_OEN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OEN_RESETVAL          (0x00000000U)

/* CFG_RGMII0_RXD2_OUT */

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD2_OUT_RESETVAL          (0x00000000U)

/* CFG_RGMII0_RXD3_IN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_IN_RESETVAL           (0x00000000U)

/* CFG_RGMII0_RXD3_OEN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OEN_RESETVAL          (0x00000000U)

/* CFG_RGMII0_RXD3_OUT */

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_RXD3_OUT_RESETVAL          (0x00000000U)

/* CFG_RGMII0_TXC_IN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_IN_RESETVAL            (0x00000000U)

/* CFG_RGMII0_TXC_OEN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OEN_RESETVAL           (0x00000000U)

/* CFG_RGMII0_TXC_OUT */

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXC_OUT_RESETVAL           (0x00000000U)

/* CFG_RGMII0_TXCTL_IN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_IN_RESETVAL          (0x00000000U)

/* CFG_RGMII0_TXCTL_OEN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OEN_RESETVAL         (0x00000000U)

/* CFG_RGMII0_TXCTL_OUT */

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXCTL_OUT_RESETVAL         (0x00000000U)

/* CFG_RGMII0_TXD0_IN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_IN_RESETVAL           (0x00000000U)

/* CFG_RGMII0_TXD0_OEN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OEN_RESETVAL          (0x00000000U)

/* CFG_RGMII0_TXD0_OUT */

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD0_OUT_RESETVAL          (0x00000000U)

/* CFG_RGMII0_TXD1_IN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_IN_RESETVAL           (0x00000000U)

/* CFG_RGMII0_TXD1_OEN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OEN_RESETVAL          (0x00000000U)

/* CFG_RGMII0_TXD1_OUT */

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD1_OUT_RESETVAL          (0x00000000U)

/* CFG_RGMII0_TXD2_IN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_IN_RESETVAL           (0x00000000U)

/* CFG_RGMII0_TXD2_OEN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OEN_RESETVAL          (0x00000000U)

/* CFG_RGMII0_TXD2_OUT */

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD2_OUT_RESETVAL          (0x00000000U)

/* CFG_RGMII0_TXD3_IN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_IN_RESETVAL           (0x00000000U)

/* CFG_RGMII0_TXD3_OEN */

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OEN_RESETVAL          (0x00000000U)

/* CFG_RGMII0_TXD3_OUT */

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RGMII0_TXD3_OUT_RESETVAL          (0x00000000U)

/* CFG_RTCK_IN */

#define CSL_IODELAYCONFIG_CFG_RTCK_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RTCK_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RTCK_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RTCK_IN_COARSE_BINARY_DELAY_MAX   (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RTCK_IN_LOCK_BIT_MASK             (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RTCK_IN_LOCK_BIT_SHIFT            (10U)
#define CSL_IODELAYCONFIG_CFG_RTCK_IN_LOCK_BIT_RESETVAL         (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RTCK_IN_LOCK_BIT_MAX              (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RTCK_IN_SIGNATURE_MASK            (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RTCK_IN_SIGNATURE_SHIFT           (11U)
#define CSL_IODELAYCONFIG_CFG_RTCK_IN_SIGNATURE_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RTCK_IN_SIGNATURE_MAX             (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RTCK_IN_RESETVAL                  (0x00000000U)

/* CFG_RTCK_OEN */

#define CSL_IODELAYCONFIG_CFG_RTCK_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RTCK_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RTCK_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RTCK_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RTCK_OEN_LOCK_BIT_MASK            (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RTCK_OEN_LOCK_BIT_SHIFT           (10U)
#define CSL_IODELAYCONFIG_CFG_RTCK_OEN_LOCK_BIT_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RTCK_OEN_LOCK_BIT_MAX             (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RTCK_OEN_SIGNATURE_MASK           (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RTCK_OEN_SIGNATURE_SHIFT          (11U)
#define CSL_IODELAYCONFIG_CFG_RTCK_OEN_SIGNATURE_RESETVAL       (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RTCK_OEN_SIGNATURE_MAX            (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RTCK_OEN_RESETVAL                 (0x00000000U)

/* CFG_RTCK_OUT */

#define CSL_IODELAYCONFIG_CFG_RTCK_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_RTCK_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_RTCK_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RTCK_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_RTCK_OUT_LOCK_BIT_MASK            (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_RTCK_OUT_LOCK_BIT_SHIFT           (10U)
#define CSL_IODELAYCONFIG_CFG_RTCK_OUT_LOCK_BIT_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RTCK_OUT_LOCK_BIT_MAX             (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_RTCK_OUT_SIGNATURE_MASK           (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_RTCK_OUT_SIGNATURE_SHIFT          (11U)
#define CSL_IODELAYCONFIG_CFG_RTCK_OUT_SIGNATURE_RESETVAL       (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_RTCK_OUT_SIGNATURE_MAX            (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_RTCK_OUT_RESETVAL                 (0x00000000U)

/* CFG_SPI1_CS0_IN */

#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_IN_RESETVAL              (0x00000000U)

/* CFG_SPI1_CS0_OEN */

#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OEN_RESETVAL             (0x00000000U)

/* CFG_SPI1_CS0_OUT */

#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS0_OUT_RESETVAL             (0x00000000U)

/* CFG_SPI1_CS1_IN */

#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_IN_RESETVAL              (0x00000000U)

/* CFG_SPI1_CS1_OEN */

#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OEN_RESETVAL             (0x00000000U)

/* CFG_SPI1_CS1_OUT */

#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS1_OUT_RESETVAL             (0x00000000U)

/* CFG_SPI1_CS2_IN */

#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_IN_RESETVAL              (0x00000000U)

/* CFG_SPI1_CS2_OEN */

#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OEN_RESETVAL             (0x00000000U)

/* CFG_SPI1_CS2_OUT */

#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS2_OUT_RESETVAL             (0x00000000U)

/* CFG_SPI1_CS3_IN */

#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_IN_RESETVAL              (0x00000000U)

/* CFG_SPI1_CS3_OEN */

#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OEN_RESETVAL             (0x00000000U)

/* CFG_SPI1_CS3_OUT */

#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_CS3_OUT_RESETVAL             (0x00000000U)

/* CFG_SPI1_D0_IN */

#define CSL_IODELAYCONFIG_CFG_SPI1_D0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_D0_IN_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_IN_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_IN_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_IN_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_D0_IN_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_IN_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_IN_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_IN_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_D0_IN_RESETVAL               (0x00000000U)

/* CFG_SPI1_D0_OEN */

#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OEN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OEN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OEN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OEN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OEN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OEN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OEN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OEN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OEN_RESETVAL              (0x00000000U)

/* CFG_SPI1_D0_OUT */

#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OUT_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OUT_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OUT_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OUT_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OUT_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OUT_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OUT_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OUT_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_D0_OUT_RESETVAL              (0x00000000U)

/* CFG_SPI1_D1_IN */

#define CSL_IODELAYCONFIG_CFG_SPI1_D1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_D1_IN_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_IN_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_IN_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_IN_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_D1_IN_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_IN_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_IN_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_IN_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_D1_IN_RESETVAL               (0x00000000U)

/* CFG_SPI1_D1_OEN */

#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OEN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OEN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OEN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OEN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OEN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OEN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OEN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OEN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OEN_RESETVAL              (0x00000000U)

/* CFG_SPI1_D1_OUT */

#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OUT_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OUT_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OUT_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OUT_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OUT_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OUT_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OUT_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OUT_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_D1_OUT_RESETVAL              (0x00000000U)

/* CFG_SPI1_SCLK_IN */

#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_IN_RESETVAL             (0x00000000U)

/* CFG_SPI1_SCLK_OEN */

#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OEN_RESETVAL            (0x00000000U)

/* CFG_SPI1_SCLK_OUT */

#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI1_SCLK_OUT_RESETVAL            (0x00000000U)

/* CFG_SPI2_CS0_IN */

#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_IN_RESETVAL              (0x00000000U)

/* CFG_SPI2_CS0_OEN */

#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OEN_RESETVAL             (0x00000000U)

/* CFG_SPI2_CS0_OUT */

#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI2_CS0_OUT_RESETVAL             (0x00000000U)

/* CFG_SPI2_D0_IN */

#define CSL_IODELAYCONFIG_CFG_SPI2_D0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI2_D0_IN_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_IN_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_IN_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_IN_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI2_D0_IN_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_IN_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_IN_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_IN_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI2_D0_IN_RESETVAL               (0x00000000U)

/* CFG_SPI2_D0_OEN */

#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OEN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OEN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OEN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OEN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OEN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OEN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OEN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OEN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OEN_RESETVAL              (0x00000000U)

/* CFG_SPI2_D0_OUT */

#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OUT_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OUT_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OUT_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OUT_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OUT_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OUT_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OUT_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OUT_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI2_D0_OUT_RESETVAL              (0x00000000U)

/* CFG_SPI2_D1_IN */

#define CSL_IODELAYCONFIG_CFG_SPI2_D1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI2_D1_IN_LOCK_BIT_MASK          (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_IN_LOCK_BIT_SHIFT         (10U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_IN_LOCK_BIT_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_IN_LOCK_BIT_MAX           (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI2_D1_IN_SIGNATURE_MASK         (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_IN_SIGNATURE_SHIFT        (11U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_IN_SIGNATURE_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_IN_SIGNATURE_MAX          (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI2_D1_IN_RESETVAL               (0x00000000U)

/* CFG_SPI2_D1_OEN */

#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OEN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OEN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OEN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OEN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OEN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OEN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OEN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OEN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OEN_RESETVAL              (0x00000000U)

/* CFG_SPI2_D1_OUT */

#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OUT_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OUT_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OUT_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OUT_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OUT_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OUT_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OUT_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OUT_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI2_D1_OUT_RESETVAL              (0x00000000U)

/* CFG_SPI2_SCLK_IN */

#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_IN_RESETVAL             (0x00000000U)

/* CFG_SPI2_SCLK_OEN */

#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OEN_RESETVAL            (0x00000000U)

/* CFG_SPI2_SCLK_OUT */

#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_SPI2_SCLK_OUT_RESETVAL            (0x00000000U)

/* CFG_TDI_IN */

#define CSL_IODELAYCONFIG_CFG_TDI_IN_COARSE_BINARY_DELAY_MASK   (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_TDI_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_TDI_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TDI_IN_COARSE_BINARY_DELAY_MAX    (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_TDI_IN_LOCK_BIT_MASK              (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_TDI_IN_LOCK_BIT_SHIFT             (10U)
#define CSL_IODELAYCONFIG_CFG_TDI_IN_LOCK_BIT_RESETVAL          (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TDI_IN_LOCK_BIT_MAX               (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_TDI_IN_SIGNATURE_MASK             (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_TDI_IN_SIGNATURE_SHIFT            (11U)
#define CSL_IODELAYCONFIG_CFG_TDI_IN_SIGNATURE_RESETVAL         (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TDI_IN_SIGNATURE_MAX              (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_TDI_IN_RESETVAL                   (0x00000000U)

/* CFG_TDI_OEN */

#define CSL_IODELAYCONFIG_CFG_TDI_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_TDI_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_TDI_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TDI_OEN_COARSE_BINARY_DELAY_MAX   (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_TDI_OEN_LOCK_BIT_MASK             (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_TDI_OEN_LOCK_BIT_SHIFT            (10U)
#define CSL_IODELAYCONFIG_CFG_TDI_OEN_LOCK_BIT_RESETVAL         (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TDI_OEN_LOCK_BIT_MAX              (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_TDI_OEN_SIGNATURE_MASK            (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_TDI_OEN_SIGNATURE_SHIFT           (11U)
#define CSL_IODELAYCONFIG_CFG_TDI_OEN_SIGNATURE_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TDI_OEN_SIGNATURE_MAX             (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_TDI_OEN_RESETVAL                  (0x00000000U)

/* CFG_TDI_OUT */

#define CSL_IODELAYCONFIG_CFG_TDI_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_TDI_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_TDI_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TDI_OUT_COARSE_BINARY_DELAY_MAX   (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_TDI_OUT_LOCK_BIT_MASK             (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_TDI_OUT_LOCK_BIT_SHIFT            (10U)
#define CSL_IODELAYCONFIG_CFG_TDI_OUT_LOCK_BIT_RESETVAL         (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TDI_OUT_LOCK_BIT_MAX              (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_TDI_OUT_SIGNATURE_MASK            (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_TDI_OUT_SIGNATURE_SHIFT           (11U)
#define CSL_IODELAYCONFIG_CFG_TDI_OUT_SIGNATURE_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TDI_OUT_SIGNATURE_MAX             (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_TDI_OUT_RESETVAL                  (0x00000000U)

/* CFG_TDO_IN */

#define CSL_IODELAYCONFIG_CFG_TDO_IN_COARSE_BINARY_DELAY_MASK   (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_TDO_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_TDO_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TDO_IN_COARSE_BINARY_DELAY_MAX    (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_TDO_IN_LOCK_BIT_MASK              (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_TDO_IN_LOCK_BIT_SHIFT             (10U)
#define CSL_IODELAYCONFIG_CFG_TDO_IN_LOCK_BIT_RESETVAL          (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TDO_IN_LOCK_BIT_MAX               (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_TDO_IN_SIGNATURE_MASK             (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_TDO_IN_SIGNATURE_SHIFT            (11U)
#define CSL_IODELAYCONFIG_CFG_TDO_IN_SIGNATURE_RESETVAL         (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TDO_IN_SIGNATURE_MAX              (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_TDO_IN_RESETVAL                   (0x00000000U)

/* CFG_TDO_OEN */

#define CSL_IODELAYCONFIG_CFG_TDO_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_TDO_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_TDO_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TDO_OEN_COARSE_BINARY_DELAY_MAX   (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_TDO_OEN_LOCK_BIT_MASK             (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_TDO_OEN_LOCK_BIT_SHIFT            (10U)
#define CSL_IODELAYCONFIG_CFG_TDO_OEN_LOCK_BIT_RESETVAL         (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TDO_OEN_LOCK_BIT_MAX              (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_TDO_OEN_SIGNATURE_MASK            (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_TDO_OEN_SIGNATURE_SHIFT           (11U)
#define CSL_IODELAYCONFIG_CFG_TDO_OEN_SIGNATURE_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TDO_OEN_SIGNATURE_MAX             (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_TDO_OEN_RESETVAL                  (0x00000000U)

/* CFG_TDO_OUT */

#define CSL_IODELAYCONFIG_CFG_TDO_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_TDO_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_TDO_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TDO_OUT_COARSE_BINARY_DELAY_MAX   (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_TDO_OUT_LOCK_BIT_MASK             (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_TDO_OUT_LOCK_BIT_SHIFT            (10U)
#define CSL_IODELAYCONFIG_CFG_TDO_OUT_LOCK_BIT_RESETVAL         (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TDO_OUT_LOCK_BIT_MAX              (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_TDO_OUT_SIGNATURE_MASK            (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_TDO_OUT_SIGNATURE_SHIFT           (11U)
#define CSL_IODELAYCONFIG_CFG_TDO_OUT_SIGNATURE_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TDO_OUT_SIGNATURE_MAX             (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_TDO_OUT_RESETVAL                  (0x00000000U)

/* CFG_TMS_IN */

#define CSL_IODELAYCONFIG_CFG_TMS_IN_COARSE_BINARY_DELAY_MASK   (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_TMS_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_TMS_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TMS_IN_COARSE_BINARY_DELAY_MAX    (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_TMS_IN_LOCK_BIT_MASK              (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_TMS_IN_LOCK_BIT_SHIFT             (10U)
#define CSL_IODELAYCONFIG_CFG_TMS_IN_LOCK_BIT_RESETVAL          (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TMS_IN_LOCK_BIT_MAX               (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_TMS_IN_SIGNATURE_MASK             (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_TMS_IN_SIGNATURE_SHIFT            (11U)
#define CSL_IODELAYCONFIG_CFG_TMS_IN_SIGNATURE_RESETVAL         (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TMS_IN_SIGNATURE_MAX              (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_TMS_IN_RESETVAL                   (0x00000000U)

/* CFG_TMS_OEN */

#define CSL_IODELAYCONFIG_CFG_TMS_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_TMS_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_TMS_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TMS_OEN_COARSE_BINARY_DELAY_MAX   (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_TMS_OEN_LOCK_BIT_MASK             (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_TMS_OEN_LOCK_BIT_SHIFT            (10U)
#define CSL_IODELAYCONFIG_CFG_TMS_OEN_LOCK_BIT_RESETVAL         (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TMS_OEN_LOCK_BIT_MAX              (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_TMS_OEN_SIGNATURE_MASK            (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_TMS_OEN_SIGNATURE_SHIFT           (11U)
#define CSL_IODELAYCONFIG_CFG_TMS_OEN_SIGNATURE_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TMS_OEN_SIGNATURE_MAX             (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_TMS_OEN_RESETVAL                  (0x00000000U)

/* CFG_TMS_OUT */

#define CSL_IODELAYCONFIG_CFG_TMS_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_TMS_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_TMS_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TMS_OUT_COARSE_BINARY_DELAY_MAX   (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_TMS_OUT_LOCK_BIT_MASK             (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_TMS_OUT_LOCK_BIT_SHIFT            (10U)
#define CSL_IODELAYCONFIG_CFG_TMS_OUT_LOCK_BIT_RESETVAL         (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TMS_OUT_LOCK_BIT_MAX              (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_TMS_OUT_SIGNATURE_MASK            (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_TMS_OUT_SIGNATURE_SHIFT           (11U)
#define CSL_IODELAYCONFIG_CFG_TMS_OUT_SIGNATURE_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TMS_OUT_SIGNATURE_MAX             (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_TMS_OUT_RESETVAL                  (0x00000000U)

/* CFG_TRSTN_IN */

#define CSL_IODELAYCONFIG_CFG_TRSTN_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_TRSTN_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_TRSTN_IN_LOCK_BIT_MASK            (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_IN_LOCK_BIT_SHIFT           (10U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_IN_LOCK_BIT_RESETVAL        (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_IN_LOCK_BIT_MAX             (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_TRSTN_IN_SIGNATURE_MASK           (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_IN_SIGNATURE_SHIFT          (11U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_IN_SIGNATURE_RESETVAL       (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_IN_SIGNATURE_MAX            (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_TRSTN_IN_RESETVAL                 (0x00000000U)

/* CFG_TRSTN_OEN */

#define CSL_IODELAYCONFIG_CFG_TRSTN_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_TRSTN_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_TRSTN_OEN_LOCK_BIT_MASK           (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_OEN_LOCK_BIT_SHIFT          (10U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_OEN_LOCK_BIT_RESETVAL       (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_OEN_LOCK_BIT_MAX            (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_TRSTN_OEN_SIGNATURE_MASK          (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_OEN_SIGNATURE_SHIFT         (11U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_OEN_SIGNATURE_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_OEN_SIGNATURE_MAX           (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_TRSTN_OEN_RESETVAL                (0x00000000U)

/* CFG_TRSTN_OUT */

#define CSL_IODELAYCONFIG_CFG_TRSTN_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_TRSTN_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_TRSTN_OUT_LOCK_BIT_MASK           (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_OUT_LOCK_BIT_SHIFT          (10U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_OUT_LOCK_BIT_RESETVAL       (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_OUT_LOCK_BIT_MAX            (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_TRSTN_OUT_SIGNATURE_MASK          (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_OUT_SIGNATURE_SHIFT         (11U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_OUT_SIGNATURE_RESETVAL      (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_TRSTN_OUT_SIGNATURE_MAX           (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_TRSTN_OUT_RESETVAL                (0x00000000U)

/* CFG_UART1_CTSN_IN */

#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_IN_RESETVAL            (0x00000000U)

/* CFG_UART1_CTSN_OEN */

#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OEN_RESETVAL           (0x00000000U)

/* CFG_UART1_CTSN_OUT */

#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART1_CTSN_OUT_RESETVAL           (0x00000000U)

/* CFG_UART1_RTSN_IN */

#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_IN_RESETVAL            (0x00000000U)

/* CFG_UART1_RTSN_OEN */

#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OEN_RESETVAL           (0x00000000U)

/* CFG_UART1_RTSN_OUT */

#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART1_RTSN_OUT_RESETVAL           (0x00000000U)

/* CFG_UART1_RXD_IN */

#define CSL_IODELAYCONFIG_CFG_UART1_RXD_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART1_RXD_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART1_RXD_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART1_RXD_IN_RESETVAL             (0x00000000U)

/* CFG_UART1_RXD_OEN */

#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OEN_RESETVAL            (0x00000000U)

/* CFG_UART1_RXD_OUT */

#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART1_RXD_OUT_RESETVAL            (0x00000000U)

/* CFG_UART1_TXD_IN */

#define CSL_IODELAYCONFIG_CFG_UART1_TXD_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART1_TXD_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART1_TXD_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART1_TXD_IN_RESETVAL             (0x00000000U)

/* CFG_UART1_TXD_OEN */

#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OEN_RESETVAL            (0x00000000U)

/* CFG_UART1_TXD_OUT */

#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART1_TXD_OUT_RESETVAL            (0x00000000U)

/* CFG_UART2_CTSN_IN */

#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_IN_RESETVAL            (0x00000000U)

/* CFG_UART2_CTSN_OEN */

#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OEN_RESETVAL           (0x00000000U)

/* CFG_UART2_CTSN_OUT */

#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART2_CTSN_OUT_RESETVAL           (0x00000000U)

/* CFG_UART2_RTSN_IN */

#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_IN_RESETVAL            (0x00000000U)

/* CFG_UART2_RTSN_OEN */

#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OEN_RESETVAL           (0x00000000U)

/* CFG_UART2_RTSN_OUT */

#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART2_RTSN_OUT_RESETVAL           (0x00000000U)

/* CFG_UART2_RXD_IN */

#define CSL_IODELAYCONFIG_CFG_UART2_RXD_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART2_RXD_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART2_RXD_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART2_RXD_IN_RESETVAL             (0x00000000U)

/* CFG_UART2_RXD_OEN */

#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OEN_RESETVAL            (0x00000000U)

/* CFG_UART2_RXD_OUT */

#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART2_RXD_OUT_RESETVAL            (0x00000000U)

/* CFG_UART2_TXD_IN */

#define CSL_IODELAYCONFIG_CFG_UART2_TXD_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART2_TXD_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART2_TXD_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART2_TXD_IN_RESETVAL             (0x00000000U)

/* CFG_UART2_TXD_OEN */

#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OEN_RESETVAL            (0x00000000U)

/* CFG_UART2_TXD_OUT */

#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART2_TXD_OUT_RESETVAL            (0x00000000U)

/* CFG_UART3_RXD_IN */

#define CSL_IODELAYCONFIG_CFG_UART3_RXD_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART3_RXD_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART3_RXD_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART3_RXD_IN_RESETVAL             (0x00000000U)

/* CFG_UART3_RXD_OEN */

#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OEN_RESETVAL            (0x00000000U)

/* CFG_UART3_RXD_OUT */

#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART3_RXD_OUT_RESETVAL            (0x00000000U)

/* CFG_UART3_TXD_IN */

#define CSL_IODELAYCONFIG_CFG_UART3_TXD_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART3_TXD_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART3_TXD_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART3_TXD_IN_RESETVAL             (0x00000000U)

/* CFG_UART3_TXD_OEN */

#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OEN_RESETVAL            (0x00000000U)

/* CFG_UART3_TXD_OUT */

#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_UART3_TXD_OUT_RESETVAL            (0x00000000U)

/* CFG_USB1_DRVVBUS_IN */

#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_IN_RESETVAL          (0x00000000U)

/* CFG_USB1_DRVVBUS_OEN */

#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OEN_RESETVAL         (0x00000000U)

/* CFG_USB1_DRVVBUS_OUT */

#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_USB1_DRVVBUS_OUT_RESETVAL         (0x00000000U)

/* CFG_USB2_DRVVBUS_IN */

#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_IN_RESETVAL          (0x00000000U)

/* CFG_USB2_DRVVBUS_OEN */

#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OEN_RESETVAL         (0x00000000U)

/* CFG_USB2_DRVVBUS_OUT */

#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_USB2_DRVVBUS_OUT_RESETVAL         (0x00000000U)

/* CFG_VIN1A_CLK0_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_IN_RESETVAL            (0x00000000U)

/* CFG_VIN1A_CLK0_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OEN_RESETVAL           (0x00000000U)

/* CFG_VIN1A_CLK0_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_CLK0_OUT_RESETVAL           (0x00000000U)

/* CFG_VIN1A_D0_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_IN_RESETVAL              (0x00000000U)

/* CFG_VIN1A_D0_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D0_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D0_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D10_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_IN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D10_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D10_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D10_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D11_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_IN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D11_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D11_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D11_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D12_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_IN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D12_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D12_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D12_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D13_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_IN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D13_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D13_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D13_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D14_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_IN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D14_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D14_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D14_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D15_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_IN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D15_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D15_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D15_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D16_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_IN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D16_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D16_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D16_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D17_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_IN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D17_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D17_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D17_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D18_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_IN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D18_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D18_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D18_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D19_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_IN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D19_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D19_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D19_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D1_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_IN_RESETVAL              (0x00000000U)

/* CFG_VIN1A_D1_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D1_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D1_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D20_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_IN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D20_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D20_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D20_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D21_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_IN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D21_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D21_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D21_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D22_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_IN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D22_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D22_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D22_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D23_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_IN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D23_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D23_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D23_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN1A_D2_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_IN_RESETVAL              (0x00000000U)

/* CFG_VIN1A_D2_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D2_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D2_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D3_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_IN_RESETVAL              (0x00000000U)

/* CFG_VIN1A_D3_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D3_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D3_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D4_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_IN_RESETVAL              (0x00000000U)

/* CFG_VIN1A_D4_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D4_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D4_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D5_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_IN_RESETVAL              (0x00000000U)

/* CFG_VIN1A_D5_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D5_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D5_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D6_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_IN_RESETVAL              (0x00000000U)

/* CFG_VIN1A_D6_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D6_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D6_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D7_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_IN_RESETVAL              (0x00000000U)

/* CFG_VIN1A_D7_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D7_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D7_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D8_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_IN_RESETVAL              (0x00000000U)

/* CFG_VIN1A_D8_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D8_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D8_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D9_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_IN_RESETVAL              (0x00000000U)

/* CFG_VIN1A_D9_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_D9_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_D9_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN1A_DE0_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_IN_RESETVAL             (0x00000000U)

/* CFG_VIN1A_DE0_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN1A_DE0_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_DE0_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN1A_FLD0_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_IN_RESETVAL            (0x00000000U)

/* CFG_VIN1A_FLD0_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OEN_RESETVAL           (0x00000000U)

/* CFG_VIN1A_FLD0_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_FLD0_OUT_RESETVAL           (0x00000000U)

/* CFG_VIN1A_HSYNC0_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_IN_RESETVAL          (0x00000000U)

/* CFG_VIN1A_HSYNC0_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OEN_RESETVAL         (0x00000000U)

/* CFG_VIN1A_HSYNC0_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_HSYNC0_OUT_RESETVAL         (0x00000000U)

/* CFG_VIN1A_VSYNC0_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_IN_RESETVAL          (0x00000000U)

/* CFG_VIN1A_VSYNC0_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OEN_RESETVAL         (0x00000000U)

/* CFG_VIN1A_VSYNC0_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1A_VSYNC0_OUT_RESETVAL         (0x00000000U)

/* CFG_VIN1B_CLK1_IN */

#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_IN_RESETVAL            (0x00000000U)

/* CFG_VIN1B_CLK1_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OEN_RESETVAL           (0x00000000U)

/* CFG_VIN1B_CLK1_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN1B_CLK1_OUT_RESETVAL           (0x00000000U)

/* CFG_VIN2A_CLK0_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_IN_RESETVAL            (0x00000000U)

/* CFG_VIN2A_CLK0_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OEN_RESETVAL           (0x00000000U)

/* CFG_VIN2A_CLK0_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_CLK0_OUT_RESETVAL           (0x00000000U)

/* CFG_VIN2A_D0_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_IN_RESETVAL              (0x00000000U)

/* CFG_VIN2A_D0_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D0_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D0_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D10_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_IN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D10_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D10_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D10_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D11_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_IN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D11_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D11_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D11_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D12_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_IN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D12_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D12_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D12_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D13_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_IN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D13_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D13_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D13_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D14_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_IN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D14_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D14_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D14_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D15_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_IN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D15_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D15_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D15_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D16_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_IN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D16_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D16_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D16_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D17_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_IN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D17_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D17_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D17_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D18_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_IN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D18_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D18_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D18_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D19_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_IN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D19_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D19_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D19_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D1_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_IN_RESETVAL              (0x00000000U)

/* CFG_VIN2A_D1_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D1_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D1_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D20_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_IN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D20_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D20_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D20_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D21_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_IN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D21_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D21_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D21_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D22_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_IN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D22_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D22_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D22_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D23_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_IN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D23_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D23_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D23_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN2A_D2_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_IN_RESETVAL              (0x00000000U)

/* CFG_VIN2A_D2_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D2_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D2_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D3_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_IN_RESETVAL              (0x00000000U)

/* CFG_VIN2A_D3_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D3_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D3_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D4_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_IN_RESETVAL              (0x00000000U)

/* CFG_VIN2A_D4_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D4_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D4_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D5_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_IN_RESETVAL              (0x00000000U)

/* CFG_VIN2A_D5_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D5_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D5_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D6_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_IN_RESETVAL              (0x00000000U)

/* CFG_VIN2A_D6_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D6_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D6_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D7_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_IN_RESETVAL              (0x00000000U)

/* CFG_VIN2A_D7_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D7_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D7_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D8_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_IN_RESETVAL              (0x00000000U)

/* CFG_VIN2A_D8_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D8_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D8_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D9_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_IN_RESETVAL              (0x00000000U)

/* CFG_VIN2A_D9_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OEN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_D9_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_D9_OUT_RESETVAL             (0x00000000U)

/* CFG_VIN2A_DE0_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_IN_RESETVAL             (0x00000000U)

/* CFG_VIN2A_DE0_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OEN_RESETVAL            (0x00000000U)

/* CFG_VIN2A_DE0_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_DE0_OUT_RESETVAL            (0x00000000U)

/* CFG_VIN2A_FLD0_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_IN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_IN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_IN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_IN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_IN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_IN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_IN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_IN_RESETVAL            (0x00000000U)

/* CFG_VIN2A_FLD0_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OEN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OEN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OEN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OEN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OEN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OEN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OEN_RESETVAL           (0x00000000U)

/* CFG_VIN2A_FLD0_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OUT_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OUT_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OUT_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OUT_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OUT_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OUT_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_FLD0_OUT_RESETVAL           (0x00000000U)

/* CFG_VIN2A_HSYNC0_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_IN_RESETVAL          (0x00000000U)

/* CFG_VIN2A_HSYNC0_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OEN_RESETVAL         (0x00000000U)

/* CFG_VIN2A_HSYNC0_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_HSYNC0_OUT_RESETVAL         (0x00000000U)

/* CFG_VIN2A_VSYNC0_IN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_IN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_IN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_IN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_IN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_IN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_IN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_IN_RESETVAL          (0x00000000U)

/* CFG_VIN2A_VSYNC0_OEN */

#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OEN_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OEN_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OEN_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OEN_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OEN_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OEN_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OEN_RESETVAL         (0x00000000U)

/* CFG_VIN2A_VSYNC0_OUT */

#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OUT_LOCK_BIT_MASK    (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OUT_LOCK_BIT_SHIFT   (10U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OUT_LOCK_BIT_MAX     (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OUT_SIGNATURE_MASK   (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OUT_SIGNATURE_SHIFT  (11U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OUT_SIGNATURE_MAX    (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VIN2A_VSYNC0_OUT_RESETVAL         (0x00000000U)

/* CFG_VOUT1_CLK_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_IN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_CLK_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OEN_RESETVAL            (0x00000000U)

/* CFG_VOUT1_CLK_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_CLK_OUT_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D0_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_IN_RESETVAL              (0x00000000U)

/* CFG_VOUT1_D0_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OEN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D0_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D0_OUT_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D10_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_IN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D10_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OEN_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D10_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D10_OUT_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D11_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_IN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D11_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OEN_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D11_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D11_OUT_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D12_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_IN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D12_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OEN_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D12_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D12_OUT_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D13_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_IN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D13_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OEN_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D13_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D13_OUT_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D14_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_IN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D14_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OEN_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D14_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D14_OUT_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D15_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_IN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D15_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OEN_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D15_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D15_OUT_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D16_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_IN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D16_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OEN_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D16_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D16_OUT_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D17_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_IN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D17_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OEN_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D17_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D17_OUT_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D18_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_IN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D18_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OEN_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D18_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D18_OUT_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D19_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_IN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D19_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OEN_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D19_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D19_OUT_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D1_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_IN_RESETVAL              (0x00000000U)

/* CFG_VOUT1_D1_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OEN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D1_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D1_OUT_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D20_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_IN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D20_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OEN_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D20_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D20_OUT_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D21_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_IN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D21_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OEN_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D21_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D21_OUT_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D22_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_IN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D22_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OEN_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D22_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D22_OUT_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D23_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_IN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D23_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OEN_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D23_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D23_OUT_RESETVAL            (0x00000000U)

/* CFG_VOUT1_D2_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_IN_RESETVAL              (0x00000000U)

/* CFG_VOUT1_D2_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OEN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D2_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D2_OUT_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D3_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_IN_RESETVAL              (0x00000000U)

/* CFG_VOUT1_D3_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OEN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D3_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D3_OUT_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D4_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_IN_RESETVAL              (0x00000000U)

/* CFG_VOUT1_D4_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OEN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D4_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D4_OUT_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D5_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_IN_RESETVAL              (0x00000000U)

/* CFG_VOUT1_D5_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OEN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D5_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D5_OUT_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D6_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_IN_RESETVAL              (0x00000000U)

/* CFG_VOUT1_D6_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OEN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D6_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D6_OUT_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D7_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_IN_RESETVAL              (0x00000000U)

/* CFG_VOUT1_D7_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OEN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D7_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D7_OUT_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D8_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_IN_RESETVAL              (0x00000000U)

/* CFG_VOUT1_D8_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OEN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D8_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D8_OUT_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D9_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_IN_RESETVAL              (0x00000000U)

/* CFG_VOUT1_D9_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OEN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_D9_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_D9_OUT_RESETVAL             (0x00000000U)

/* CFG_VOUT1_DE_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_IN_LOCK_BIT_MASK         (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_IN_LOCK_BIT_SHIFT        (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_IN_LOCK_BIT_RESETVAL     (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_IN_LOCK_BIT_MAX          (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_IN_SIGNATURE_MASK        (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_IN_SIGNATURE_SHIFT       (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_IN_SIGNATURE_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_IN_SIGNATURE_MAX         (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_IN_RESETVAL              (0x00000000U)

/* CFG_VOUT1_DE_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OEN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OEN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OEN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OEN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OEN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OEN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OEN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OEN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OEN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_DE_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OUT_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OUT_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OUT_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OUT_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OUT_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OUT_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OUT_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OUT_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_DE_OUT_RESETVAL             (0x00000000U)

/* CFG_VOUT1_FLD_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_IN_RESETVAL             (0x00000000U)

/* CFG_VOUT1_FLD_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OEN_RESETVAL            (0x00000000U)

/* CFG_VOUT1_FLD_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_FLD_OUT_RESETVAL            (0x00000000U)

/* CFG_VOUT1_HSYNC_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_IN_RESETVAL           (0x00000000U)

/* CFG_VOUT1_HSYNC_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OEN_RESETVAL          (0x00000000U)

/* CFG_VOUT1_HSYNC_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_HSYNC_OUT_RESETVAL          (0x00000000U)

/* CFG_VOUT1_VSYNC_IN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_IN_LOCK_BIT_MASK      (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_IN_LOCK_BIT_SHIFT     (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_IN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_IN_LOCK_BIT_MAX       (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_IN_SIGNATURE_MASK     (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_IN_SIGNATURE_SHIFT    (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_IN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_IN_SIGNATURE_MAX      (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_IN_RESETVAL           (0x00000000U)

/* CFG_VOUT1_VSYNC_OEN */

#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OEN_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OEN_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OEN_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OEN_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OEN_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OEN_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OEN_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OEN_RESETVAL          (0x00000000U)

/* CFG_VOUT1_VSYNC_OUT */

#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OUT_LOCK_BIT_MASK     (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OUT_LOCK_BIT_SHIFT    (10U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OUT_LOCK_BIT_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OUT_LOCK_BIT_MAX      (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OUT_SIGNATURE_MASK    (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OUT_SIGNATURE_SHIFT   (11U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OUT_SIGNATURE_MAX     (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_VOUT1_VSYNC_OUT_RESETVAL          (0x00000000U)

/* CFG_XREF_CLK0_IN */

#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_IN_RESETVAL             (0x00000000U)

/* CFG_XREF_CLK0_OEN */

#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OEN_RESETVAL            (0x00000000U)

/* CFG_XREF_CLK0_OUT */

#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK0_OUT_RESETVAL            (0x00000000U)

/* CFG_XREF_CLK1_IN */

#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_IN_RESETVAL             (0x00000000U)

/* CFG_XREF_CLK1_OEN */

#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OEN_RESETVAL            (0x00000000U)

/* CFG_XREF_CLK1_OUT */

#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK1_OUT_RESETVAL            (0x00000000U)

/* CFG_XREF_CLK2_IN */

#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_IN_RESETVAL             (0x00000000U)

/* CFG_XREF_CLK2_OEN */

#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OEN_RESETVAL            (0x00000000U)

/* CFG_XREF_CLK2_OUT */

#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK2_OUT_RESETVAL            (0x00000000U)

/* CFG_XREF_CLK3_IN */

#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_IN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_IN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_IN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_IN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_IN_LOCK_BIT_MASK        (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_IN_LOCK_BIT_SHIFT       (10U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_IN_LOCK_BIT_RESETVAL    (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_IN_LOCK_BIT_MAX         (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_IN_SIGNATURE_MASK       (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_IN_SIGNATURE_SHIFT      (11U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_IN_SIGNATURE_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_IN_SIGNATURE_MAX        (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_IN_RESETVAL             (0x00000000U)

/* CFG_XREF_CLK3_OEN */

#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OEN_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OEN_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OEN_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OEN_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OEN_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OEN_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OEN_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OEN_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OEN_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OEN_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OEN_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OEN_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OEN_RESETVAL            (0x00000000U)

/* CFG_XREF_CLK3_OUT */

#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OUT_COARSE_BINARY_DELAY_MASK  (0x000003FFU)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OUT_COARSE_BINARY_DELAY_SHIFT  (0U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OUT_COARSE_BINARY_DELAY_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OUT_COARSE_BINARY_DELAY_MAX  (0x000003ffU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OUT_LOCK_BIT_MASK       (0x00000400U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OUT_LOCK_BIT_SHIFT      (10U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OUT_LOCK_BIT_RESETVAL   (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OUT_LOCK_BIT_MAX        (0x00000001U)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OUT_SIGNATURE_MASK      (0x0001F800U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OUT_SIGNATURE_SHIFT     (11U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OUT_SIGNATURE_RESETVAL  (0x00000000U)
#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OUT_SIGNATURE_MAX       (0x0000003fU)

#define CSL_IODELAYCONFIG_CFG_XREF_CLK3_OUT_RESETVAL            (0x00000000U)

#ifdef __cplusplus
}
#endif
#endif
