/*******************************************************************************
* File Name: cyfitter.h
* 
* PSoC Creator  4.2
*
* Description:
* 
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, 
* disclaimers, and limitations in the end user license agreement accompanying 
* the software package with which this file was provided.
********************************************************************************/

#ifndef INCLUDED_CYFITTER_H
#define INCLUDED_CYFITTER_H
#include "cydevice_trm.h"

/* LCD_Char_LCDPort */
#define LCD_Char_LCDPort__0__DM__MASK 0x07u
#define LCD_Char_LCDPort__0__DM__SHIFT 0u
#define LCD_Char_LCDPort__0__DR CYREG_PRT0_DR
#define LCD_Char_LCDPort__0__HSIOM CYREG_HSIOM_PORT_SEL0
#define LCD_Char_LCDPort__0__HSIOM_MASK 0x0000000Fu
#define LCD_Char_LCDPort__0__HSIOM_SHIFT 0u
#define LCD_Char_LCDPort__0__INTCFG CYREG_PRT0_INTCFG
#define LCD_Char_LCDPort__0__INTSTAT CYREG_PRT0_INTSTAT
#define LCD_Char_LCDPort__0__MASK 0x01u
#define LCD_Char_LCDPort__0__PA__CFG0 CYREG_UDB_PA0_CFG0
#define LCD_Char_LCDPort__0__PA__CFG1 CYREG_UDB_PA0_CFG1
#define LCD_Char_LCDPort__0__PA__CFG10 CYREG_UDB_PA0_CFG10
#define LCD_Char_LCDPort__0__PA__CFG11 CYREG_UDB_PA0_CFG11
#define LCD_Char_LCDPort__0__PA__CFG12 CYREG_UDB_PA0_CFG12
#define LCD_Char_LCDPort__0__PA__CFG13 CYREG_UDB_PA0_CFG13
#define LCD_Char_LCDPort__0__PA__CFG14 CYREG_UDB_PA0_CFG14
#define LCD_Char_LCDPort__0__PA__CFG2 CYREG_UDB_PA0_CFG2
#define LCD_Char_LCDPort__0__PA__CFG3 CYREG_UDB_PA0_CFG3
#define LCD_Char_LCDPort__0__PA__CFG4 CYREG_UDB_PA0_CFG4
#define LCD_Char_LCDPort__0__PA__CFG5 CYREG_UDB_PA0_CFG5
#define LCD_Char_LCDPort__0__PA__CFG6 CYREG_UDB_PA0_CFG6
#define LCD_Char_LCDPort__0__PA__CFG7 CYREG_UDB_PA0_CFG7
#define LCD_Char_LCDPort__0__PA__CFG8 CYREG_UDB_PA0_CFG8
#define LCD_Char_LCDPort__0__PA__CFG9 CYREG_UDB_PA0_CFG9
#define LCD_Char_LCDPort__0__PC CYREG_PRT0_PC
#define LCD_Char_LCDPort__0__PC2 CYREG_PRT0_PC2
#define LCD_Char_LCDPort__0__PORT 0u
#define LCD_Char_LCDPort__0__PS CYREG_PRT0_PS
#define LCD_Char_LCDPort__0__SHIFT 0u
#define LCD_Char_LCDPort__1__DM__MASK 0x38u
#define LCD_Char_LCDPort__1__DM__SHIFT 3u
#define LCD_Char_LCDPort__1__DR CYREG_PRT0_DR
#define LCD_Char_LCDPort__1__HSIOM CYREG_HSIOM_PORT_SEL0
#define LCD_Char_LCDPort__1__HSIOM_MASK 0x000000F0u
#define LCD_Char_LCDPort__1__HSIOM_SHIFT 4u
#define LCD_Char_LCDPort__1__INTCFG CYREG_PRT0_INTCFG
#define LCD_Char_LCDPort__1__INTSTAT CYREG_PRT0_INTSTAT
#define LCD_Char_LCDPort__1__MASK 0x02u
#define LCD_Char_LCDPort__1__PA__CFG0 CYREG_UDB_PA0_CFG0
#define LCD_Char_LCDPort__1__PA__CFG1 CYREG_UDB_PA0_CFG1
#define LCD_Char_LCDPort__1__PA__CFG10 CYREG_UDB_PA0_CFG10
#define LCD_Char_LCDPort__1__PA__CFG11 CYREG_UDB_PA0_CFG11
#define LCD_Char_LCDPort__1__PA__CFG12 CYREG_UDB_PA0_CFG12
#define LCD_Char_LCDPort__1__PA__CFG13 CYREG_UDB_PA0_CFG13
#define LCD_Char_LCDPort__1__PA__CFG14 CYREG_UDB_PA0_CFG14
#define LCD_Char_LCDPort__1__PA__CFG2 CYREG_UDB_PA0_CFG2
#define LCD_Char_LCDPort__1__PA__CFG3 CYREG_UDB_PA0_CFG3
#define LCD_Char_LCDPort__1__PA__CFG4 CYREG_UDB_PA0_CFG4
#define LCD_Char_LCDPort__1__PA__CFG5 CYREG_UDB_PA0_CFG5
#define LCD_Char_LCDPort__1__PA__CFG6 CYREG_UDB_PA0_CFG6
#define LCD_Char_LCDPort__1__PA__CFG7 CYREG_UDB_PA0_CFG7
#define LCD_Char_LCDPort__1__PA__CFG8 CYREG_UDB_PA0_CFG8
#define LCD_Char_LCDPort__1__PA__CFG9 CYREG_UDB_PA0_CFG9
#define LCD_Char_LCDPort__1__PC CYREG_PRT0_PC
#define LCD_Char_LCDPort__1__PC2 CYREG_PRT0_PC2
#define LCD_Char_LCDPort__1__PORT 0u
#define LCD_Char_LCDPort__1__PS CYREG_PRT0_PS
#define LCD_Char_LCDPort__1__SHIFT 1u
#define LCD_Char_LCDPort__2__DM__MASK 0x1C0u
#define LCD_Char_LCDPort__2__DM__SHIFT 6u
#define LCD_Char_LCDPort__2__DR CYREG_PRT0_DR
#define LCD_Char_LCDPort__2__HSIOM CYREG_HSIOM_PORT_SEL0
#define LCD_Char_LCDPort__2__HSIOM_MASK 0x00000F00u
#define LCD_Char_LCDPort__2__HSIOM_SHIFT 8u
#define LCD_Char_LCDPort__2__INTCFG CYREG_PRT0_INTCFG
#define LCD_Char_LCDPort__2__INTSTAT CYREG_PRT0_INTSTAT
#define LCD_Char_LCDPort__2__MASK 0x04u
#define LCD_Char_LCDPort__2__PA__CFG0 CYREG_UDB_PA0_CFG0
#define LCD_Char_LCDPort__2__PA__CFG1 CYREG_UDB_PA0_CFG1
#define LCD_Char_LCDPort__2__PA__CFG10 CYREG_UDB_PA0_CFG10
#define LCD_Char_LCDPort__2__PA__CFG11 CYREG_UDB_PA0_CFG11
#define LCD_Char_LCDPort__2__PA__CFG12 CYREG_UDB_PA0_CFG12
#define LCD_Char_LCDPort__2__PA__CFG13 CYREG_UDB_PA0_CFG13
#define LCD_Char_LCDPort__2__PA__CFG14 CYREG_UDB_PA0_CFG14
#define LCD_Char_LCDPort__2__PA__CFG2 CYREG_UDB_PA0_CFG2
#define LCD_Char_LCDPort__2__PA__CFG3 CYREG_UDB_PA0_CFG3
#define LCD_Char_LCDPort__2__PA__CFG4 CYREG_UDB_PA0_CFG4
#define LCD_Char_LCDPort__2__PA__CFG5 CYREG_UDB_PA0_CFG5
#define LCD_Char_LCDPort__2__PA__CFG6 CYREG_UDB_PA0_CFG6
#define LCD_Char_LCDPort__2__PA__CFG7 CYREG_UDB_PA0_CFG7
#define LCD_Char_LCDPort__2__PA__CFG8 CYREG_UDB_PA0_CFG8
#define LCD_Char_LCDPort__2__PA__CFG9 CYREG_UDB_PA0_CFG9
#define LCD_Char_LCDPort__2__PC CYREG_PRT0_PC
#define LCD_Char_LCDPort__2__PC2 CYREG_PRT0_PC2
#define LCD_Char_LCDPort__2__PORT 0u
#define LCD_Char_LCDPort__2__PS CYREG_PRT0_PS
#define LCD_Char_LCDPort__2__SHIFT 2u
#define LCD_Char_LCDPort__3__DM__MASK 0xE00u
#define LCD_Char_LCDPort__3__DM__SHIFT 9u
#define LCD_Char_LCDPort__3__DR CYREG_PRT0_DR
#define LCD_Char_LCDPort__3__HSIOM CYREG_HSIOM_PORT_SEL0
#define LCD_Char_LCDPort__3__HSIOM_MASK 0x0000F000u
#define LCD_Char_LCDPort__3__HSIOM_SHIFT 12u
#define LCD_Char_LCDPort__3__INTCFG CYREG_PRT0_INTCFG
#define LCD_Char_LCDPort__3__INTSTAT CYREG_PRT0_INTSTAT
#define LCD_Char_LCDPort__3__MASK 0x08u
#define LCD_Char_LCDPort__3__PA__CFG0 CYREG_UDB_PA0_CFG0
#define LCD_Char_LCDPort__3__PA__CFG1 CYREG_UDB_PA0_CFG1
#define LCD_Char_LCDPort__3__PA__CFG10 CYREG_UDB_PA0_CFG10
#define LCD_Char_LCDPort__3__PA__CFG11 CYREG_UDB_PA0_CFG11
#define LCD_Char_LCDPort__3__PA__CFG12 CYREG_UDB_PA0_CFG12
#define LCD_Char_LCDPort__3__PA__CFG13 CYREG_UDB_PA0_CFG13
#define LCD_Char_LCDPort__3__PA__CFG14 CYREG_UDB_PA0_CFG14
#define LCD_Char_LCDPort__3__PA__CFG2 CYREG_UDB_PA0_CFG2
#define LCD_Char_LCDPort__3__PA__CFG3 CYREG_UDB_PA0_CFG3
#define LCD_Char_LCDPort__3__PA__CFG4 CYREG_UDB_PA0_CFG4
#define LCD_Char_LCDPort__3__PA__CFG5 CYREG_UDB_PA0_CFG5
#define LCD_Char_LCDPort__3__PA__CFG6 CYREG_UDB_PA0_CFG6
#define LCD_Char_LCDPort__3__PA__CFG7 CYREG_UDB_PA0_CFG7
#define LCD_Char_LCDPort__3__PA__CFG8 CYREG_UDB_PA0_CFG8
#define LCD_Char_LCDPort__3__PA__CFG9 CYREG_UDB_PA0_CFG9
#define LCD_Char_LCDPort__3__PC CYREG_PRT0_PC
#define LCD_Char_LCDPort__3__PC2 CYREG_PRT0_PC2
#define LCD_Char_LCDPort__3__PORT 0u
#define LCD_Char_LCDPort__3__PS CYREG_PRT0_PS
#define LCD_Char_LCDPort__3__SHIFT 3u
#define LCD_Char_LCDPort__4__DM__MASK 0x7000u
#define LCD_Char_LCDPort__4__DM__SHIFT 12u
#define LCD_Char_LCDPort__4__DR CYREG_PRT0_DR
#define LCD_Char_LCDPort__4__HSIOM CYREG_HSIOM_PORT_SEL0
#define LCD_Char_LCDPort__4__HSIOM_MASK 0x000F0000u
#define LCD_Char_LCDPort__4__HSIOM_SHIFT 16u
#define LCD_Char_LCDPort__4__INTCFG CYREG_PRT0_INTCFG
#define LCD_Char_LCDPort__4__INTSTAT CYREG_PRT0_INTSTAT
#define LCD_Char_LCDPort__4__MASK 0x10u
#define LCD_Char_LCDPort__4__PA__CFG0 CYREG_UDB_PA0_CFG0
#define LCD_Char_LCDPort__4__PA__CFG1 CYREG_UDB_PA0_CFG1
#define LCD_Char_LCDPort__4__PA__CFG10 CYREG_UDB_PA0_CFG10
#define LCD_Char_LCDPort__4__PA__CFG11 CYREG_UDB_PA0_CFG11
#define LCD_Char_LCDPort__4__PA__CFG12 CYREG_UDB_PA0_CFG12
#define LCD_Char_LCDPort__4__PA__CFG13 CYREG_UDB_PA0_CFG13
#define LCD_Char_LCDPort__4__PA__CFG14 CYREG_UDB_PA0_CFG14
#define LCD_Char_LCDPort__4__PA__CFG2 CYREG_UDB_PA0_CFG2
#define LCD_Char_LCDPort__4__PA__CFG3 CYREG_UDB_PA0_CFG3
#define LCD_Char_LCDPort__4__PA__CFG4 CYREG_UDB_PA0_CFG4
#define LCD_Char_LCDPort__4__PA__CFG5 CYREG_UDB_PA0_CFG5
#define LCD_Char_LCDPort__4__PA__CFG6 CYREG_UDB_PA0_CFG6
#define LCD_Char_LCDPort__4__PA__CFG7 CYREG_UDB_PA0_CFG7
#define LCD_Char_LCDPort__4__PA__CFG8 CYREG_UDB_PA0_CFG8
#define LCD_Char_LCDPort__4__PA__CFG9 CYREG_UDB_PA0_CFG9
#define LCD_Char_LCDPort__4__PC CYREG_PRT0_PC
#define LCD_Char_LCDPort__4__PC2 CYREG_PRT0_PC2
#define LCD_Char_LCDPort__4__PORT 0u
#define LCD_Char_LCDPort__4__PS CYREG_PRT0_PS
#define LCD_Char_LCDPort__4__SHIFT 4u
#define LCD_Char_LCDPort__5__DM__MASK 0x38000u
#define LCD_Char_LCDPort__5__DM__SHIFT 15u
#define LCD_Char_LCDPort__5__DR CYREG_PRT0_DR
#define LCD_Char_LCDPort__5__HSIOM CYREG_HSIOM_PORT_SEL0
#define LCD_Char_LCDPort__5__HSIOM_MASK 0x00F00000u
#define LCD_Char_LCDPort__5__HSIOM_SHIFT 20u
#define LCD_Char_LCDPort__5__INTCFG CYREG_PRT0_INTCFG
#define LCD_Char_LCDPort__5__INTSTAT CYREG_PRT0_INTSTAT
#define LCD_Char_LCDPort__5__MASK 0x20u
#define LCD_Char_LCDPort__5__PA__CFG0 CYREG_UDB_PA0_CFG0
#define LCD_Char_LCDPort__5__PA__CFG1 CYREG_UDB_PA0_CFG1
#define LCD_Char_LCDPort__5__PA__CFG10 CYREG_UDB_PA0_CFG10
#define LCD_Char_LCDPort__5__PA__CFG11 CYREG_UDB_PA0_CFG11
#define LCD_Char_LCDPort__5__PA__CFG12 CYREG_UDB_PA0_CFG12
#define LCD_Char_LCDPort__5__PA__CFG13 CYREG_UDB_PA0_CFG13
#define LCD_Char_LCDPort__5__PA__CFG14 CYREG_UDB_PA0_CFG14
#define LCD_Char_LCDPort__5__PA__CFG2 CYREG_UDB_PA0_CFG2
#define LCD_Char_LCDPort__5__PA__CFG3 CYREG_UDB_PA0_CFG3
#define LCD_Char_LCDPort__5__PA__CFG4 CYREG_UDB_PA0_CFG4
#define LCD_Char_LCDPort__5__PA__CFG5 CYREG_UDB_PA0_CFG5
#define LCD_Char_LCDPort__5__PA__CFG6 CYREG_UDB_PA0_CFG6
#define LCD_Char_LCDPort__5__PA__CFG7 CYREG_UDB_PA0_CFG7
#define LCD_Char_LCDPort__5__PA__CFG8 CYREG_UDB_PA0_CFG8
#define LCD_Char_LCDPort__5__PA__CFG9 CYREG_UDB_PA0_CFG9
#define LCD_Char_LCDPort__5__PC CYREG_PRT0_PC
#define LCD_Char_LCDPort__5__PC2 CYREG_PRT0_PC2
#define LCD_Char_LCDPort__5__PORT 0u
#define LCD_Char_LCDPort__5__PS CYREG_PRT0_PS
#define LCD_Char_LCDPort__5__SHIFT 5u
#define LCD_Char_LCDPort__6__DM__MASK 0x1C0000u
#define LCD_Char_LCDPort__6__DM__SHIFT 18u
#define LCD_Char_LCDPort__6__DR CYREG_PRT0_DR
#define LCD_Char_LCDPort__6__HSIOM CYREG_HSIOM_PORT_SEL0
#define LCD_Char_LCDPort__6__HSIOM_MASK 0x0F000000u
#define LCD_Char_LCDPort__6__HSIOM_SHIFT 24u
#define LCD_Char_LCDPort__6__INTCFG CYREG_PRT0_INTCFG
#define LCD_Char_LCDPort__6__INTSTAT CYREG_PRT0_INTSTAT
#define LCD_Char_LCDPort__6__MASK 0x40u
#define LCD_Char_LCDPort__6__PA__CFG0 CYREG_UDB_PA0_CFG0
#define LCD_Char_LCDPort__6__PA__CFG1 CYREG_UDB_PA0_CFG1
#define LCD_Char_LCDPort__6__PA__CFG10 CYREG_UDB_PA0_CFG10
#define LCD_Char_LCDPort__6__PA__CFG11 CYREG_UDB_PA0_CFG11
#define LCD_Char_LCDPort__6__PA__CFG12 CYREG_UDB_PA0_CFG12
#define LCD_Char_LCDPort__6__PA__CFG13 CYREG_UDB_PA0_CFG13
#define LCD_Char_LCDPort__6__PA__CFG14 CYREG_UDB_PA0_CFG14
#define LCD_Char_LCDPort__6__PA__CFG2 CYREG_UDB_PA0_CFG2
#define LCD_Char_LCDPort__6__PA__CFG3 CYREG_UDB_PA0_CFG3
#define LCD_Char_LCDPort__6__PA__CFG4 CYREG_UDB_PA0_CFG4
#define LCD_Char_LCDPort__6__PA__CFG5 CYREG_UDB_PA0_CFG5
#define LCD_Char_LCDPort__6__PA__CFG6 CYREG_UDB_PA0_CFG6
#define LCD_Char_LCDPort__6__PA__CFG7 CYREG_UDB_PA0_CFG7
#define LCD_Char_LCDPort__6__PA__CFG8 CYREG_UDB_PA0_CFG8
#define LCD_Char_LCDPort__6__PA__CFG9 CYREG_UDB_PA0_CFG9
#define LCD_Char_LCDPort__6__PC CYREG_PRT0_PC
#define LCD_Char_LCDPort__6__PC2 CYREG_PRT0_PC2
#define LCD_Char_LCDPort__6__PORT 0u
#define LCD_Char_LCDPort__6__PS CYREG_PRT0_PS
#define LCD_Char_LCDPort__6__SHIFT 6u
#define LCD_Char_LCDPort__DR CYREG_PRT0_DR
#define LCD_Char_LCDPort__INTCFG CYREG_PRT0_INTCFG
#define LCD_Char_LCDPort__INTSTAT CYREG_PRT0_INTSTAT
#define LCD_Char_LCDPort__MASK 0x7Fu
#define LCD_Char_LCDPort__PA__CFG0 CYREG_UDB_PA0_CFG0
#define LCD_Char_LCDPort__PA__CFG1 CYREG_UDB_PA0_CFG1
#define LCD_Char_LCDPort__PA__CFG10 CYREG_UDB_PA0_CFG10
#define LCD_Char_LCDPort__PA__CFG11 CYREG_UDB_PA0_CFG11
#define LCD_Char_LCDPort__PA__CFG12 CYREG_UDB_PA0_CFG12
#define LCD_Char_LCDPort__PA__CFG13 CYREG_UDB_PA0_CFG13
#define LCD_Char_LCDPort__PA__CFG14 CYREG_UDB_PA0_CFG14
#define LCD_Char_LCDPort__PA__CFG2 CYREG_UDB_PA0_CFG2
#define LCD_Char_LCDPort__PA__CFG3 CYREG_UDB_PA0_CFG3
#define LCD_Char_LCDPort__PA__CFG4 CYREG_UDB_PA0_CFG4
#define LCD_Char_LCDPort__PA__CFG5 CYREG_UDB_PA0_CFG5
#define LCD_Char_LCDPort__PA__CFG6 CYREG_UDB_PA0_CFG6
#define LCD_Char_LCDPort__PA__CFG7 CYREG_UDB_PA0_CFG7
#define LCD_Char_LCDPort__PA__CFG8 CYREG_UDB_PA0_CFG8
#define LCD_Char_LCDPort__PA__CFG9 CYREG_UDB_PA0_CFG9
#define LCD_Char_LCDPort__PC CYREG_PRT0_PC
#define LCD_Char_LCDPort__PC2 CYREG_PRT0_PC2
#define LCD_Char_LCDPort__PORT 0u
#define LCD_Char_LCDPort__PS CYREG_PRT0_PS
#define LCD_Char_LCDPort__SHIFT 0u

/* Pin */
#define Pin__0__DM__MASK 0x38000u
#define Pin__0__DM__SHIFT 15u
#define Pin__0__DR CYREG_PRT2_DR
#define Pin__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define Pin__0__HSIOM_MASK 0x00F00000u
#define Pin__0__HSIOM_SHIFT 20u
#define Pin__0__INTCFG CYREG_PRT2_INTCFG
#define Pin__0__INTSTAT CYREG_PRT2_INTSTAT
#define Pin__0__MASK 0x20u
#define Pin__0__PA__CFG0 CYREG_UDB_PA2_CFG0
#define Pin__0__PA__CFG1 CYREG_UDB_PA2_CFG1
#define Pin__0__PA__CFG10 CYREG_UDB_PA2_CFG10
#define Pin__0__PA__CFG11 CYREG_UDB_PA2_CFG11
#define Pin__0__PA__CFG12 CYREG_UDB_PA2_CFG12
#define Pin__0__PA__CFG13 CYREG_UDB_PA2_CFG13
#define Pin__0__PA__CFG14 CYREG_UDB_PA2_CFG14
#define Pin__0__PA__CFG2 CYREG_UDB_PA2_CFG2
#define Pin__0__PA__CFG3 CYREG_UDB_PA2_CFG3
#define Pin__0__PA__CFG4 CYREG_UDB_PA2_CFG4
#define Pin__0__PA__CFG5 CYREG_UDB_PA2_CFG5
#define Pin__0__PA__CFG6 CYREG_UDB_PA2_CFG6
#define Pin__0__PA__CFG7 CYREG_UDB_PA2_CFG7
#define Pin__0__PA__CFG8 CYREG_UDB_PA2_CFG8
#define Pin__0__PA__CFG9 CYREG_UDB_PA2_CFG9
#define Pin__0__PC CYREG_PRT2_PC
#define Pin__0__PC2 CYREG_PRT2_PC2
#define Pin__0__PORT 2u
#define Pin__0__PS CYREG_PRT2_PS
#define Pin__0__SHIFT 5u
#define Pin__DR CYREG_PRT2_DR
#define Pin__INTCFG CYREG_PRT2_INTCFG
#define Pin__INTSTAT CYREG_PRT2_INTSTAT
#define Pin__MASK 0x20u
#define Pin__PA__CFG0 CYREG_UDB_PA2_CFG0
#define Pin__PA__CFG1 CYREG_UDB_PA2_CFG1
#define Pin__PA__CFG10 CYREG_UDB_PA2_CFG10
#define Pin__PA__CFG11 CYREG_UDB_PA2_CFG11
#define Pin__PA__CFG12 CYREG_UDB_PA2_CFG12
#define Pin__PA__CFG13 CYREG_UDB_PA2_CFG13
#define Pin__PA__CFG14 CYREG_UDB_PA2_CFG14
#define Pin__PA__CFG2 CYREG_UDB_PA2_CFG2
#define Pin__PA__CFG3 CYREG_UDB_PA2_CFG3
#define Pin__PA__CFG4 CYREG_UDB_PA2_CFG4
#define Pin__PA__CFG5 CYREG_UDB_PA2_CFG5
#define Pin__PA__CFG6 CYREG_UDB_PA2_CFG6
#define Pin__PA__CFG7 CYREG_UDB_PA2_CFG7
#define Pin__PA__CFG8 CYREG_UDB_PA2_CFG8
#define Pin__PA__CFG9 CYREG_UDB_PA2_CFG9
#define Pin__PC CYREG_PRT2_PC
#define Pin__PC2 CYREG_PRT2_PC2
#define Pin__PORT 2u
#define Pin__PS CYREG_PRT2_PS
#define Pin__SHIFT 5u
#define Pin_Switch__0__DM__MASK 0xE00000u
#define Pin_Switch__0__DM__SHIFT 21u
#define Pin_Switch__0__DR CYREG_PRT0_DR
#define Pin_Switch__0__HSIOM CYREG_HSIOM_PORT_SEL0
#define Pin_Switch__0__HSIOM_MASK 0xF0000000u
#define Pin_Switch__0__HSIOM_SHIFT 28u
#define Pin_Switch__0__INTCFG CYREG_PRT0_INTCFG
#define Pin_Switch__0__INTSTAT CYREG_PRT0_INTSTAT
#define Pin_Switch__0__MASK 0x80u
#define Pin_Switch__0__PA__CFG0 CYREG_UDB_PA0_CFG0
#define Pin_Switch__0__PA__CFG1 CYREG_UDB_PA0_CFG1
#define Pin_Switch__0__PA__CFG10 CYREG_UDB_PA0_CFG10
#define Pin_Switch__0__PA__CFG11 CYREG_UDB_PA0_CFG11
#define Pin_Switch__0__PA__CFG12 CYREG_UDB_PA0_CFG12
#define Pin_Switch__0__PA__CFG13 CYREG_UDB_PA0_CFG13
#define Pin_Switch__0__PA__CFG14 CYREG_UDB_PA0_CFG14
#define Pin_Switch__0__PA__CFG2 CYREG_UDB_PA0_CFG2
#define Pin_Switch__0__PA__CFG3 CYREG_UDB_PA0_CFG3
#define Pin_Switch__0__PA__CFG4 CYREG_UDB_PA0_CFG4
#define Pin_Switch__0__PA__CFG5 CYREG_UDB_PA0_CFG5
#define Pin_Switch__0__PA__CFG6 CYREG_UDB_PA0_CFG6
#define Pin_Switch__0__PA__CFG7 CYREG_UDB_PA0_CFG7
#define Pin_Switch__0__PA__CFG8 CYREG_UDB_PA0_CFG8
#define Pin_Switch__0__PA__CFG9 CYREG_UDB_PA0_CFG9
#define Pin_Switch__0__PC CYREG_PRT0_PC
#define Pin_Switch__0__PC2 CYREG_PRT0_PC2
#define Pin_Switch__0__PORT 0u
#define Pin_Switch__0__PS CYREG_PRT0_PS
#define Pin_Switch__0__SHIFT 7u
#define Pin_Switch__DR CYREG_PRT0_DR
#define Pin_Switch__INTCFG CYREG_PRT0_INTCFG
#define Pin_Switch__INTSTAT CYREG_PRT0_INTSTAT
#define Pin_Switch__MASK 0x80u
#define Pin_Switch__PA__CFG0 CYREG_UDB_PA0_CFG0
#define Pin_Switch__PA__CFG1 CYREG_UDB_PA0_CFG1
#define Pin_Switch__PA__CFG10 CYREG_UDB_PA0_CFG10
#define Pin_Switch__PA__CFG11 CYREG_UDB_PA0_CFG11
#define Pin_Switch__PA__CFG12 CYREG_UDB_PA0_CFG12
#define Pin_Switch__PA__CFG13 CYREG_UDB_PA0_CFG13
#define Pin_Switch__PA__CFG14 CYREG_UDB_PA0_CFG14
#define Pin_Switch__PA__CFG2 CYREG_UDB_PA0_CFG2
#define Pin_Switch__PA__CFG3 CYREG_UDB_PA0_CFG3
#define Pin_Switch__PA__CFG4 CYREG_UDB_PA0_CFG4
#define Pin_Switch__PA__CFG5 CYREG_UDB_PA0_CFG5
#define Pin_Switch__PA__CFG6 CYREG_UDB_PA0_CFG6
#define Pin_Switch__PA__CFG7 CYREG_UDB_PA0_CFG7
#define Pin_Switch__PA__CFG8 CYREG_UDB_PA0_CFG8
#define Pin_Switch__PA__CFG9 CYREG_UDB_PA0_CFG9
#define Pin_Switch__PC CYREG_PRT0_PC
#define Pin_Switch__PC2 CYREG_PRT0_PC2
#define Pin_Switch__PORT 0u
#define Pin_Switch__PS CYREG_PRT0_PS
#define Pin_Switch__SHIFT 7u

/* Rx */
#define Rx__0__DM__MASK 0x1C0u
#define Rx__0__DM__SHIFT 6u
#define Rx__0__DR CYREG_PRT2_DR
#define Rx__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define Rx__0__HSIOM_MASK 0x00000F00u
#define Rx__0__HSIOM_SHIFT 8u
#define Rx__0__INTCFG CYREG_PRT2_INTCFG
#define Rx__0__INTSTAT CYREG_PRT2_INTSTAT
#define Rx__0__MASK 0x04u
#define Rx__0__PA__CFG0 CYREG_UDB_PA2_CFG0
#define Rx__0__PA__CFG1 CYREG_UDB_PA2_CFG1
#define Rx__0__PA__CFG10 CYREG_UDB_PA2_CFG10
#define Rx__0__PA__CFG11 CYREG_UDB_PA2_CFG11
#define Rx__0__PA__CFG12 CYREG_UDB_PA2_CFG12
#define Rx__0__PA__CFG13 CYREG_UDB_PA2_CFG13
#define Rx__0__PA__CFG14 CYREG_UDB_PA2_CFG14
#define Rx__0__PA__CFG2 CYREG_UDB_PA2_CFG2
#define Rx__0__PA__CFG3 CYREG_UDB_PA2_CFG3
#define Rx__0__PA__CFG4 CYREG_UDB_PA2_CFG4
#define Rx__0__PA__CFG5 CYREG_UDB_PA2_CFG5
#define Rx__0__PA__CFG6 CYREG_UDB_PA2_CFG6
#define Rx__0__PA__CFG7 CYREG_UDB_PA2_CFG7
#define Rx__0__PA__CFG8 CYREG_UDB_PA2_CFG8
#define Rx__0__PA__CFG9 CYREG_UDB_PA2_CFG9
#define Rx__0__PC CYREG_PRT2_PC
#define Rx__0__PC2 CYREG_PRT2_PC2
#define Rx__0__PORT 2u
#define Rx__0__PS CYREG_PRT2_PS
#define Rx__0__SHIFT 2u
#define Rx__DR CYREG_PRT2_DR
#define Rx__INTCFG CYREG_PRT2_INTCFG
#define Rx__INTSTAT CYREG_PRT2_INTSTAT
#define Rx__MASK 0x04u
#define Rx__PA__CFG0 CYREG_UDB_PA2_CFG0
#define Rx__PA__CFG1 CYREG_UDB_PA2_CFG1
#define Rx__PA__CFG10 CYREG_UDB_PA2_CFG10
#define Rx__PA__CFG11 CYREG_UDB_PA2_CFG11
#define Rx__PA__CFG12 CYREG_UDB_PA2_CFG12
#define Rx__PA__CFG13 CYREG_UDB_PA2_CFG13
#define Rx__PA__CFG14 CYREG_UDB_PA2_CFG14
#define Rx__PA__CFG2 CYREG_UDB_PA2_CFG2
#define Rx__PA__CFG3 CYREG_UDB_PA2_CFG3
#define Rx__PA__CFG4 CYREG_UDB_PA2_CFG4
#define Rx__PA__CFG5 CYREG_UDB_PA2_CFG5
#define Rx__PA__CFG6 CYREG_UDB_PA2_CFG6
#define Rx__PA__CFG7 CYREG_UDB_PA2_CFG7
#define Rx__PA__CFG8 CYREG_UDB_PA2_CFG8
#define Rx__PA__CFG9 CYREG_UDB_PA2_CFG9
#define Rx__PC CYREG_PRT2_PC
#define Rx__PC2 CYREG_PRT2_PC2
#define Rx__PORT 2u
#define Rx__PS CYREG_PRT2_PS
#define Rx__SHIFT 2u

/* Tx */
#define Tx__0__DM__MASK 0xE00u
#define Tx__0__DM__SHIFT 9u
#define Tx__0__DR CYREG_PRT1_DR
#define Tx__0__HSIOM CYREG_HSIOM_PORT_SEL1
#define Tx__0__HSIOM_MASK 0x0000F000u
#define Tx__0__HSIOM_SHIFT 12u
#define Tx__0__INTCFG CYREG_PRT1_INTCFG
#define Tx__0__INTSTAT CYREG_PRT1_INTSTAT
#define Tx__0__MASK 0x08u
#define Tx__0__OUT_SEL CYREG_UDB_PA1_CFG10
#define Tx__0__OUT_SEL_SHIFT 6u
#define Tx__0__OUT_SEL_VAL 3u
#define Tx__0__PA__CFG0 CYREG_UDB_PA1_CFG0
#define Tx__0__PA__CFG1 CYREG_UDB_PA1_CFG1
#define Tx__0__PA__CFG10 CYREG_UDB_PA1_CFG10
#define Tx__0__PA__CFG11 CYREG_UDB_PA1_CFG11
#define Tx__0__PA__CFG12 CYREG_UDB_PA1_CFG12
#define Tx__0__PA__CFG13 CYREG_UDB_PA1_CFG13
#define Tx__0__PA__CFG14 CYREG_UDB_PA1_CFG14
#define Tx__0__PA__CFG2 CYREG_UDB_PA1_CFG2
#define Tx__0__PA__CFG3 CYREG_UDB_PA1_CFG3
#define Tx__0__PA__CFG4 CYREG_UDB_PA1_CFG4
#define Tx__0__PA__CFG5 CYREG_UDB_PA1_CFG5
#define Tx__0__PA__CFG6 CYREG_UDB_PA1_CFG6
#define Tx__0__PA__CFG7 CYREG_UDB_PA1_CFG7
#define Tx__0__PA__CFG8 CYREG_UDB_PA1_CFG8
#define Tx__0__PA__CFG9 CYREG_UDB_PA1_CFG9
#define Tx__0__PC CYREG_PRT1_PC
#define Tx__0__PC2 CYREG_PRT1_PC2
#define Tx__0__PORT 1u
#define Tx__0__PS CYREG_PRT1_PS
#define Tx__0__SHIFT 3u
#define Tx__DR CYREG_PRT1_DR
#define Tx__INTCFG CYREG_PRT1_INTCFG
#define Tx__INTSTAT CYREG_PRT1_INTSTAT
#define Tx__MASK 0x08u
#define Tx__PA__CFG0 CYREG_UDB_PA1_CFG0
#define Tx__PA__CFG1 CYREG_UDB_PA1_CFG1
#define Tx__PA__CFG10 CYREG_UDB_PA1_CFG10
#define Tx__PA__CFG11 CYREG_UDB_PA1_CFG11
#define Tx__PA__CFG12 CYREG_UDB_PA1_CFG12
#define Tx__PA__CFG13 CYREG_UDB_PA1_CFG13
#define Tx__PA__CFG14 CYREG_UDB_PA1_CFG14
#define Tx__PA__CFG2 CYREG_UDB_PA1_CFG2
#define Tx__PA__CFG3 CYREG_UDB_PA1_CFG3
#define Tx__PA__CFG4 CYREG_UDB_PA1_CFG4
#define Tx__PA__CFG5 CYREG_UDB_PA1_CFG5
#define Tx__PA__CFG6 CYREG_UDB_PA1_CFG6
#define Tx__PA__CFG7 CYREG_UDB_PA1_CFG7
#define Tx__PA__CFG8 CYREG_UDB_PA1_CFG8
#define Tx__PA__CFG9 CYREG_UDB_PA1_CFG9
#define Tx__PC CYREG_PRT1_PC
#define Tx__PC2 CYREG_PRT1_PC2
#define Tx__PORT 1u
#define Tx__PS CYREG_PRT1_PS
#define Tx__SHIFT 3u

/* UART_BUART */
#define UART_BUART_sRX_RxBitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_UDB_W16_ACTL_02
#define UART_BUART_sRX_RxBitCounter__16BIT_CONTROL_CONTROL_REG CYREG_UDB_W16_CTL_02
#define UART_BUART_sRX_RxBitCounter__16BIT_CONTROL_COUNT_REG CYREG_UDB_W16_CTL_02
#define UART_BUART_sRX_RxBitCounter__16BIT_COUNT_CONTROL_REG CYREG_UDB_W16_CTL_02
#define UART_BUART_sRX_RxBitCounter__16BIT_COUNT_COUNT_REG CYREG_UDB_W16_CTL_02
#define UART_BUART_sRX_RxBitCounter__16BIT_MASK_MASK_REG CYREG_UDB_W16_MSK_02
#define UART_BUART_sRX_RxBitCounter__16BIT_MASK_PERIOD_REG CYREG_UDB_W16_MSK_02
#define UART_BUART_sRX_RxBitCounter__16BIT_PERIOD_MASK_REG CYREG_UDB_W16_MSK_02
#define UART_BUART_sRX_RxBitCounter__16BIT_PERIOD_PERIOD_REG CYREG_UDB_W16_MSK_02
#define UART_BUART_sRX_RxBitCounter__CONTROL_AUX_CTL_REG CYREG_UDB_W8_ACTL_02
#define UART_BUART_sRX_RxBitCounter__CONTROL_REG CYREG_UDB_W8_CTL_02
#define UART_BUART_sRX_RxBitCounter__CONTROL_ST_REG CYREG_UDB_CAT16_CTL_ST_02
#define UART_BUART_sRX_RxBitCounter__COUNT_REG CYREG_UDB_W8_CTL_02
#define UART_BUART_sRX_RxBitCounter__COUNT_ST_REG CYREG_UDB_CAT16_CTL_ST_02
#define UART_BUART_sRX_RxBitCounter__MASK_CTL_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK_02
#define UART_BUART_sRX_RxBitCounter__PER_CTL_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK_02
#define UART_BUART_sRX_RxBitCounter__PERIOD_REG CYREG_UDB_W8_MSK_02
#define UART_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_UDB_W16_ACTL_02
#define UART_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_REG CYREG_UDB_W16_ST_02
#define UART_BUART_sRX_RxBitCounter_ST__MASK_REG CYREG_UDB_W8_MSK_02
#define UART_BUART_sRX_RxBitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK_02
#define UART_BUART_sRX_RxBitCounter_ST__PER_ST_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK_02
#define UART_BUART_sRX_RxBitCounter_ST__STATUS_AUX_CTL_REG CYREG_UDB_W8_ACTL_02
#define UART_BUART_sRX_RxBitCounter_ST__STATUS_CNT_REG CYREG_UDB_CAT16_CTL_ST_02
#define UART_BUART_sRX_RxBitCounter_ST__STATUS_CONTROL_REG CYREG_UDB_CAT16_CTL_ST_02
#define UART_BUART_sRX_RxBitCounter_ST__STATUS_REG CYREG_UDB_W8_ST_02
#define UART_BUART_sRX_RxShifter_u0__16BIT_A0_REG CYREG_UDB_W16_A0_02
#define UART_BUART_sRX_RxShifter_u0__16BIT_A1_REG CYREG_UDB_W16_A1_02
#define UART_BUART_sRX_RxShifter_u0__16BIT_D0_REG CYREG_UDB_W16_D0_02
#define UART_BUART_sRX_RxShifter_u0__16BIT_D1_REG CYREG_UDB_W16_D1_02
#define UART_BUART_sRX_RxShifter_u0__16BIT_DP_AUX_CTL_REG CYREG_UDB_W16_ACTL_02
#define UART_BUART_sRX_RxShifter_u0__16BIT_F0_REG CYREG_UDB_W16_F0_02
#define UART_BUART_sRX_RxShifter_u0__16BIT_F1_REG CYREG_UDB_W16_F1_02
#define UART_BUART_sRX_RxShifter_u0__A0_A1_REG CYREG_UDB_CAT16_A_02
#define UART_BUART_sRX_RxShifter_u0__A0_REG CYREG_UDB_W8_A0_02
#define UART_BUART_sRX_RxShifter_u0__A1_REG CYREG_UDB_W8_A1_02
#define UART_BUART_sRX_RxShifter_u0__D0_D1_REG CYREG_UDB_CAT16_D_02
#define UART_BUART_sRX_RxShifter_u0__D0_REG CYREG_UDB_W8_D0_02
#define UART_BUART_sRX_RxShifter_u0__D1_REG CYREG_UDB_W8_D1_02
#define UART_BUART_sRX_RxShifter_u0__DP_AUX_CTL_REG CYREG_UDB_W8_ACTL_02
#define UART_BUART_sRX_RxShifter_u0__F0_F1_REG CYREG_UDB_CAT16_F_02
#define UART_BUART_sRX_RxShifter_u0__F0_REG CYREG_UDB_W8_F0_02
#define UART_BUART_sRX_RxShifter_u0__F1_REG CYREG_UDB_W8_F1_02
#define UART_BUART_sRX_RxShifter_u0__MSK_DP_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK_02
#define UART_BUART_sRX_RxShifter_u0__PER_DP_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK_02
#define UART_BUART_sRX_RxSts__3__MASK 0x08u
#define UART_BUART_sRX_RxSts__3__POS 3
#define UART_BUART_sRX_RxSts__4__MASK 0x10u
#define UART_BUART_sRX_RxSts__4__POS 4
#define UART_BUART_sRX_RxSts__5__MASK 0x20u
#define UART_BUART_sRX_RxSts__5__POS 5
#define UART_BUART_sRX_RxSts__MASK 0x38u
#define UART_BUART_sRX_RxSts__MASK_REG CYREG_UDB_W8_MSK_03
#define UART_BUART_sRX_RxSts__STATUS_AUX_CTL_REG CYREG_UDB_W8_ACTL_03
#define UART_BUART_sRX_RxSts__STATUS_REG CYREG_UDB_W8_ST_03
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG CYREG_UDB_W16_A0_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG CYREG_UDB_W16_A1_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG CYREG_UDB_W16_D0_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG CYREG_UDB_W16_D1_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG CYREG_UDB_W16_ACTL_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG CYREG_UDB_W16_F0_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG CYREG_UDB_W16_F1_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__32BIT_A0_REG CYREG_UDB_W32_A0_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__32BIT_A1_REG CYREG_UDB_W32_A1_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__32BIT_D0_REG CYREG_UDB_W32_D0_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__32BIT_D1_REG CYREG_UDB_W32_D1_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__32BIT_DP_AUX_CTL_REG CYREG_UDB_W32_ACTL_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__32BIT_F0_REG CYREG_UDB_W32_F0_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__32BIT_F1_REG CYREG_UDB_W32_F1_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG CYREG_UDB_CAT16_A_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG CYREG_UDB_W8_A0_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG CYREG_UDB_W8_A1_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG CYREG_UDB_CAT16_D_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG CYREG_UDB_W8_D0_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG CYREG_UDB_W8_D1_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG CYREG_UDB_W8_ACTL_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG CYREG_UDB_CAT16_F_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG CYREG_UDB_W8_F0_00
#define UART_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG CYREG_UDB_W8_F1_00
#define UART_BUART_sTX_TxShifter_u0__16BIT_A0_REG CYREG_UDB_W16_A0_01
#define UART_BUART_sTX_TxShifter_u0__16BIT_A1_REG CYREG_UDB_W16_A1_01
#define UART_BUART_sTX_TxShifter_u0__16BIT_D0_REG CYREG_UDB_W16_D0_01
#define UART_BUART_sTX_TxShifter_u0__16BIT_D1_REG CYREG_UDB_W16_D1_01
#define UART_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG CYREG_UDB_W16_ACTL_01
#define UART_BUART_sTX_TxShifter_u0__16BIT_F0_REG CYREG_UDB_W16_F0_01
#define UART_BUART_sTX_TxShifter_u0__16BIT_F1_REG CYREG_UDB_W16_F1_01
#define UART_BUART_sTX_TxShifter_u0__A0_A1_REG CYREG_UDB_CAT16_A_01
#define UART_BUART_sTX_TxShifter_u0__A0_REG CYREG_UDB_W8_A0_01
#define UART_BUART_sTX_TxShifter_u0__A1_REG CYREG_UDB_W8_A1_01
#define UART_BUART_sTX_TxShifter_u0__D0_D1_REG CYREG_UDB_CAT16_D_01
#define UART_BUART_sTX_TxShifter_u0__D0_REG CYREG_UDB_W8_D0_01
#define UART_BUART_sTX_TxShifter_u0__D1_REG CYREG_UDB_W8_D1_01
#define UART_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG CYREG_UDB_W8_ACTL_01
#define UART_BUART_sTX_TxShifter_u0__F0_F1_REG CYREG_UDB_CAT16_F_01
#define UART_BUART_sTX_TxShifter_u0__F0_REG CYREG_UDB_W8_F0_01
#define UART_BUART_sTX_TxShifter_u0__F1_REG CYREG_UDB_W8_F1_01
#define UART_BUART_sTX_TxSts__0__MASK 0x01u
#define UART_BUART_sTX_TxSts__0__POS 0
#define UART_BUART_sTX_TxSts__1__MASK 0x02u
#define UART_BUART_sTX_TxSts__1__POS 1
#define UART_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG CYREG_UDB_W16_ACTL_01
#define UART_BUART_sTX_TxSts__16BIT_STATUS_REG CYREG_UDB_W16_ST_01
#define UART_BUART_sTX_TxSts__2__MASK 0x04u
#define UART_BUART_sTX_TxSts__2__POS 2
#define UART_BUART_sTX_TxSts__3__MASK 0x08u
#define UART_BUART_sTX_TxSts__3__POS 3
#define UART_BUART_sTX_TxSts__MASK 0x0Fu
#define UART_BUART_sTX_TxSts__MASK_REG CYREG_UDB_W8_MSK_01
#define UART_BUART_sTX_TxSts__STATUS_AUX_CTL_REG CYREG_UDB_W8_ACTL_01
#define UART_BUART_sTX_TxSts__STATUS_REG CYREG_UDB_W8_ST_01

/* UART_IntClock */
#define UART_IntClock__DIVIDER_MASK 0x0000FFFFu
#define UART_IntClock__ENABLE CYREG_CLK_DIVIDER_A00
#define UART_IntClock__ENABLE_MASK 0x80000000u
#define UART_IntClock__MASK 0x80000000u
#define UART_IntClock__REGISTER CYREG_CLK_DIVIDER_A00

/* UART_RXInternalInterrupt */
#define UART_RXInternalInterrupt__INTC_CLR_EN_REG CYREG_CM0_ICER
#define UART_RXInternalInterrupt__INTC_CLR_PD_REG CYREG_CM0_ICPR
#define UART_RXInternalInterrupt__INTC_MASK 0x01u
#define UART_RXInternalInterrupt__INTC_NUMBER 0u
#define UART_RXInternalInterrupt__INTC_PRIOR_MASK 0xC0u
#define UART_RXInternalInterrupt__INTC_PRIOR_NUM 3u
#define UART_RXInternalInterrupt__INTC_PRIOR_REG CYREG_CM0_IPR0
#define UART_RXInternalInterrupt__INTC_SET_EN_REG CYREG_CM0_ISER
#define UART_RXInternalInterrupt__INTC_SET_PD_REG CYREG_CM0_ISPR

/* UART_TXInternalInterrupt */
#define UART_TXInternalInterrupt__INTC_CLR_EN_REG CYREG_CM0_ICER
#define UART_TXInternalInterrupt__INTC_CLR_PD_REG CYREG_CM0_ICPR
#define UART_TXInternalInterrupt__INTC_MASK 0x04u
#define UART_TXInternalInterrupt__INTC_NUMBER 2u
#define UART_TXInternalInterrupt__INTC_PRIOR_MASK 0xC00000u
#define UART_TXInternalInterrupt__INTC_PRIOR_NUM 3u
#define UART_TXInternalInterrupt__INTC_PRIOR_REG CYREG_CM0_IPR0
#define UART_TXInternalInterrupt__INTC_SET_EN_REG CYREG_CM0_ISER
#define UART_TXInternalInterrupt__INTC_SET_PD_REG CYREG_CM0_ISPR

/* Miscellaneous */
#define CY_PROJECT_NAME "UART_Bootloader_Host"
#define CY_VERSION "PSoC Creator  4.2"
#define CYDEV_BANDGAP_VOLTAGE 1.024
#define CYDEV_BCLK__HFCLK__HZ 24000000U
#define CYDEV_BCLK__HFCLK__KHZ 24000U
#define CYDEV_BCLK__HFCLK__MHZ 24U
#define CYDEV_BCLK__SYSCLK__HZ 24000000U
#define CYDEV_BCLK__SYSCLK__KHZ 24000U
#define CYDEV_BCLK__SYSCLK__MHZ 24U
#define CYDEV_CHIP_DIE_LEOPARD 1u
#define CYDEV_CHIP_DIE_PSOC4A 18u
#define CYDEV_CHIP_DIE_PSOC5LP 2u
#define CYDEV_CHIP_DIE_PSOC5TM 3u
#define CYDEV_CHIP_DIE_TMA4 4u
#define CYDEV_CHIP_DIE_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_FM0P 5u
#define CYDEV_CHIP_FAMILY_FM3 6u
#define CYDEV_CHIP_FAMILY_FM4 7u
#define CYDEV_CHIP_FAMILY_PSOC3 1u
#define CYDEV_CHIP_FAMILY_PSOC4 2u
#define CYDEV_CHIP_FAMILY_PSOC5 3u
#define CYDEV_CHIP_FAMILY_PSOC6 4u
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC4
#define CYDEV_CHIP_JTAG_ID 0x04C81193u
#define CYDEV_CHIP_MEMBER_3A 1u
#define CYDEV_CHIP_MEMBER_4A 18u
#define CYDEV_CHIP_MEMBER_4D 13u
#define CYDEV_CHIP_MEMBER_4E 6u
#define CYDEV_CHIP_MEMBER_4F 19u
#define CYDEV_CHIP_MEMBER_4G 4u
#define CYDEV_CHIP_MEMBER_4H 17u
#define CYDEV_CHIP_MEMBER_4I 23u
#define CYDEV_CHIP_MEMBER_4J 14u
#define CYDEV_CHIP_MEMBER_4K 15u
#define CYDEV_CHIP_MEMBER_4L 22u
#define CYDEV_CHIP_MEMBER_4M 21u
#define CYDEV_CHIP_MEMBER_4N 10u
#define CYDEV_CHIP_MEMBER_4O 7u
#define CYDEV_CHIP_MEMBER_4P 20u
#define CYDEV_CHIP_MEMBER_4Q 12u
#define CYDEV_CHIP_MEMBER_4R 8u
#define CYDEV_CHIP_MEMBER_4S 11u
#define CYDEV_CHIP_MEMBER_4T 9u
#define CYDEV_CHIP_MEMBER_4U 5u
#define CYDEV_CHIP_MEMBER_4V 16u
#define CYDEV_CHIP_MEMBER_5A 3u
#define CYDEV_CHIP_MEMBER_5B 2u
#define CYDEV_CHIP_MEMBER_6A 24u
#define CYDEV_CHIP_MEMBER_FM3 28u
#define CYDEV_CHIP_MEMBER_FM4 29u
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 25u
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 26u
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 27u
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_4A
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
#define CYDEV_CHIP_REV_PSOC5TM_ES0 0u
#define CYDEV_CHIP_REV_PSOC5TM_ES1 1u
#define CYDEV_CHIP_REV_PSOC5TM_PRODUCTION 1u
#define CYDEV_CHIP_REV_TMA4_ES 17u
#define CYDEV_CHIP_REV_TMA4_ES2 33u
#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_3A_ES1 0u
#define CYDEV_CHIP_REVISION_3A_ES2 1u
#define CYDEV_CHIP_REVISION_3A_ES3 3u
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
#define CYDEV_CHIP_REVISION_4A_ES0 17u
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD 0u
#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u
#define CYDEV_CHIP_REVISION_4G_ES 17u
#define CYDEV_CHIP_REVISION_4G_ES2 33u
#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4I_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4J_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4K_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4T_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4V_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_5A_ES0 0u
#define CYDEV_CHIP_REVISION_5A_ES1 1u
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
#define CYDEV_CHIP_REVISION_5B_ES0 0u
#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_6A_ES 17u
#define CYDEV_CHIP_REVISION_6A_NO_UDB 33u
#define CYDEV_CHIP_REVISION_6A_PRODUCTION 33u
#define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_4A_PRODUCTION
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
#define CYDEV_CONFIG_READ_ACCELERATOR 1
#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
#define CYDEV_CONFIGURATION_COMPRESSED 1
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
#define CYDEV_CONFIGURATION_MODE_DMA 2
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
#define CYDEV_DEBUG_PROTECT_KILL 4
#define CYDEV_DEBUG_PROTECT_OPEN 1
#define CYDEV_DEBUG_PROTECT CYDEV_DEBUG_PROTECT_OPEN
#define CYDEV_DEBUG_PROTECT_PROTECTED 2
#define CYDEV_DEBUGGING_DPS_Disable 3
#define CYDEV_DEBUGGING_DPS_SWD 2
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD
#define CYDEV_DEBUGGING_ENABLE 1
#define CYDEV_DFT_SELECT_CLK0 1u
#define CYDEV_DFT_SELECT_CLK1 2u
#define CYDEV_HEAP_SIZE 0x80
#define CYDEV_IMO_TRIMMED_BY_USB 0u
#define CYDEV_IMO_TRIMMED_BY_WCO 0u
#define CYDEV_IS_EXPORTING_CODE 0
#define CYDEV_IS_IMPORTING_CODE 0
#define CYDEV_PROJ_TYPE 0
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LAUNCHER 5
#define CYDEV_PROJ_TYPE_LOADABLE 2
#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
#define CYDEV_PROJ_TYPE_STANDARD 0
#define CYDEV_STACK_SIZE 0x0400
#define CYDEV_USE_BUNDLED_CMSIS 1
#define CYDEV_VARIABLE_VDDA 0
#define CYDEV_VDDA 5
#define CYDEV_VDDA_MV 5000
#define CYDEV_VDDD 5
#define CYDEV_VDDD_MV 5000
#define CYDEV_WDT_GENERATE_ISR 0u
#define CYIPBLOCK_M0S8_CTBM_VERSION 0
#define CYIPBLOCK_m0s8cpuss_VERSION 0
#define CYIPBLOCK_m0s8csd_VERSION 0
#define CYIPBLOCK_m0s8gpio2_VERSION 0
#define CYIPBLOCK_m0s8hsiom4a_VERSION 0
#define CYIPBLOCK_m0s8lcd_VERSION 0
#define CYIPBLOCK_m0s8lpcomp_VERSION 0
#define CYIPBLOCK_m0s8pclk_VERSION 0
#define CYIPBLOCK_m0s8sar_VERSION 0
#define CYIPBLOCK_m0s8scb_VERSION 0
#define CYIPBLOCK_m0s8srssv2_VERSION 1
#define CYIPBLOCK_m0s8tcpwm_VERSION 0
#define CYIPBLOCK_m0s8udbif_VERSION 0
#define CYIPBLOCK_S8_GPIO_VERSION 2
#define CYDEV_BOOTLOADER_ENABLE 0

#endif /* INCLUDED_CYFITTER_H */
